System fails to produce data output — flip-flops test OK individually A multistage sequential circuit produces no data output. Each flip-flop checks OK with a logic probe and pulser when tested individually. Which fault could still explain the system-level failure?

Introduction / Context:
Troubleshooting sequential logic requires distinguishing device-level health from system-level connectivity. A logic probe and pulser can verify that each flip-flop toggles when stimulated directly, yet the overall chain may still fail due to faults in shared resources (like the clock) or broken links between stages. Recognizing symptoms that point to a global timing path problem is a key diagnostic skill.

Given Data / Assumptions:

• No overall data output is observed at the system output node.
• Each flip-flop responds correctly when locally pulsed at its input/clock during isolated tests.
• Interconnections and the common system clock distribute signals between stages under normal operation.

Concept / Approach:

If a clock input line is open (broken trace, bad via, cracked solder joint), stages will not receive legitimate clock transitions, so they will never advance during system operation. Local testing with a hand pulser can bypass the broken clock path, making each flip-flop appear healthy in isolation and masking the real fault. This discrepancy between local OK tests and global failure is a hallmark of a missing common stimulus.

Step-by-Step Solution:

Verification / Alternative check:

Probe the clock at each stage; the missing edge will reveal where the line is open. Wiggling or thermal stressing the board may intermittently restore contact, further indicating a cracked joint or via.

Why Other Options Are Wrong:

Data output line grounded: would show a hard LOW even during local pulsing at the last stage; the prompt suggests all FFs appear to work when pulsed.

Interconnect line shorted to ground: a direct short on a data link would also defeat local pulsing across that link; such a fault typically manifests during the isolated test.

Solder bridge to Vcc on a flip-flop input: this would usually prevent correct local toggling on that device during probe/pulser tests.

Common Pitfalls:

Testing only at device pins without verifying the shared clock/enable network; overlooking hairline cracks that behave intermittently; forgetting to check connectors or jumpers that distribute the master clock.

Final Answer:

One of the clock input lines may be open.