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- Question
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
Options- A. 1100
- B. 0011
- C. 0000
- D. 1111
- Correct Answer
- 0000
- 1. The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses?
Options- A. 10011100
- B. 11000000
- C. 00001100
- D. 11110000 Discuss
- 2. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________.
Options- A. 01110
- B. 00001
- C. 00101
- D. 00110 Discuss
- 3. To operate correctly, starting a ring shift counter requires:
Options- A. clearing all the flip-flops
- B. presetting one flip-flop and clearing all others
- C. clearing one flip-flop and presetting all others
- D. presetting all the flip-flops Discuss
- 4. When the output of a tristate shift register is disabled, the output level is placed in a:
Options- A. float state
- B. LOW state
- C. high-impedance state
- D. float or high-impedance state Discuss
- 5. When is it important to use a three-state buffer?
Options- A. when two or more outputs are connected to the same input
- B. when all outputs are normally HIGH
- C. when all outputs are normally LOW
- D. when two or more outputs are connected to two or more inputs Discuss
- 6. On the third clock pulse, a 4-bit Johnson sequence is Q0 = 1, Q1 = 1, Q2 = 1, and Q3 = 0. On the fourth clock pulse, the sequence is ________.
Options- A. Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1
- B. Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0
- C. Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
- D. Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0 Discuss
- 7. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ________.
Options- A. 10111000
- B. 10110111
- C. 11110000
- D. 11111100 Discuss
- 8. What is meant by parallel load of a shift register?
Options- A. All FFs are preset with data.
- B. Each FF is loaded with data, one at a time. Discuss
- 9. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________.
Options- A. 4 ?s
- B. 40 ?s
- C. 400 ?s
- D. 40 ms Discuss
- 10. What does the output enable do on the 74395A chip?
Options- A. It determines when data can be loaded.
- B. It forces all outputs to go HIGH.
- C. It forces all outputs to go LOW.
- D. It activates the three-state buffer. Discuss
Shift Registers problems
Search Results
Correct Answer: 11000000
Correct Answer: 00101
Correct Answer: presetting one flip-flop and clearing all others
Correct Answer: float or high-impedance state
Correct Answer: when two or more outputs are connected to the same input
Correct Answer: Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1
Correct Answer: 11111100
Correct Answer: All FFs are preset with data.
Correct Answer: 40 ?s
Correct Answer: It activates the three-state buffer.
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