Parallel in / Parallel out (PIPO) shift register – effect of clocking after a parallel load A 4-bit PIPO register is loaded with D3 D2 D1 D0 = 0 1 1 1 (i.e., D0 = 1, D1 = 1, D2 = 1, D3 = 0). After three left-shifts on the subsequent clock pulses (zero fill), what are Q3 Q2 Q1 Q0?

Introduction / Context:
Many parallel-access registers support both a parallel load and shift operations. This question checks whether you can track the bit pattern through several left shifts after an initial parallel load.

Given Data / Assumptions:

• Initial parallel load: Q3 Q2 Q1 Q0 = 0 1 1 1 (from D3=0, D2=1, D1=1, D0=1).
• Three left shifts are applied on subsequent clock pulses.
• On left shift, zero is shifted into Q0 (zero fill).
• No additional loads during the three clocks.

Concept / Approach:
A left shift moves each bit toward the MSB. Q3 is discarded each shift, Q0 receives a zero. Track the pattern step by step for three clocks.

Step-by-Step Solution:

Verification / Alternative check:
Count the number of ones: initially three ones. After three left shifts with zero fill in a 4-bit word, only the most significant position remains 1 and the rest become 0, giving 1000 as obtained.

Why Other Options Are Wrong:

• 1110: This is the result after a single left shift, not after three shifts.
• 0001: Would correspond to three right shifts with zero fill from 0111, not left shifts.
• 1100: This is the state after two left shifts, not three.

Common Pitfalls:

• Confusing left shift with right shift direction.
• Assuming circular rotation; here, it is a shift with zero fill, not a rotate.
• Forgetting that the parallel load sets the starting Q3..Q0.

Final Answer:
1000