Curioustab
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Home
»
Digital Electronics
»
Shift Registers
What does the output enable do on the 74395A chip?
It determines when data can be loaded.
It forces all outputs to go HIGH.
It forces all outputs to go LOW.
It activates the three-state buffer.
Correct Answer:
It activates the three-state buffer.
← Previous Question
Next Question→
More Questions from
Shift Registers
If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse?
What is a transceiver circuit?
In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________.
An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?
A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
When an 8-bit serial in/serial out shift register is used for a 20 µs time delay, the clock frequency is ________.
Another way to connect devices to a shared data bus is to use a ________.
A 74HC195 4-bit parallel access shift register can be used for ________.
The primary purpose of a three-state buffer is usually:
In a 4-bit Johnson counter sequence there are a total of how many states, or bit patterns?
Discussion & Comments
No comments yet. Be the first to comment!
Name:
Comment:
Post Comment
Join Discussion
Discussion & Comments