Programmable Logic Device Questions

• The MAX+PLUS II compiler will automatically program a macrocell to borrow up to six product terms from each of three adjacent macrocells in the same LAB.
• VHDL code is divided into three sections: library declaration, entity declaration, and architecture body.
• The JTAG signals are named TDI, TDO, TMS, and TCK.
• A GAL is a programmable/reprogrammable PAL.
• A PAL consists of an array of fixed AND gates that are connected to a programmable array of OR gates.
• Schematic capture is a process performed by PLD software.
• An expensive form of programmable logic is SPLD.
• The GAL16V8 has eight dedicated input pins.
• PLDs did not gain widespread acceptance with digital until the mid-1980s, when a device called a PAL was introduced.
• In the FLEX10K device, the LE can produce two outputs to drive local (LAB) and global (fast track) interconnects on the chip.
• Xilinx software uses triangular symbols called buffers to define pins as input or output.
• The architecture of a PAL differs slightly from that of a PROM.
• The Altera FLEX10K family uses a look-up table (LUT) architecture.
• Generally, PLDs can be described as being one of four different types.
• Altera Corporation and Xilinx Corporation are the two leading PLD manufacturers.
• The Altera UPIX educational development board contains an EP10K60 device in a 280-pin package.
• The GAL16V8 has 32 input variables.
• CPLDs and FPGAs are often referred to as high-capacity programmable logic devices (HCPLDs).
• The four input-only pins found on devices in the MAX7000S family can be configured as specific high-speed control signals or as general user inputs.
• Based on the high-density architecture of logic cells, FLEX10K devices are generally classified as HCPLDs.