The fan-out of CMOS gates is frequency dependent.

More Questions from Integrated-Circuit Logic Families

• The 74XX series TTL operates using saturated switching in which many of the transistors, when conducting, will be in the saturated condition.
• The maximum current for a LOW output on a standard TTL gate is 100 µA.
• A major drawback in using ECL logic circuits in conjunction with TTL and MOS circuits is its negative supply voltages and logic levels.
• Integrated injection logic offers high component density and is easier to fabricate than TTL.
• The noise immunity of a logic circuit refers to the circuit's ability to tolerate noise by causing spurious charges in the output voltage.
• A current-sourcing transistor may also be referred to as a pull-down transistor.
• An unused input of a NAND gate can be left unconnected, pulled high by a pull-up resistor and tied together with another input and not change the logic output.
• The major advantage of CMOS logic circuits over TTL is very low power consumption.
• The abbreviated designator for a HIGH input voltage is VIH.
• CMOS stands for "complementary metal-oxide semiconductors" and the FETs are normally enhancement mode devices.

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