Question 1

ALU control basics: The mode control pin of an arithmetic/logic unit (ALU) selects which class of operation?

Accepted Answer

Introduction / Context: An arithmetic/logic unit (ALU) is the computational core of a CPU or datapath. It typically supports both arithmetic functions (add, subtract) and logic functions (AND, OR, XOR). Many classic ALUs expose a mode control that selects between these classes. Given Data / Assumptions: A single mode input pin on the ALU. Binary selection between operation groups. Concept / Approach: ALU operation is determined by control signals. A mode pin often gates internal multiplexers to route either arithmetic carry chains or pure logic networks to the output. Thus the pin chooses the operational class, while additional function selects choose the specific operation within the class. Step-by-Step Solution: Interpret the mode pin as a high-level selector.Mode = 0 → arithmetic path (e.g., add/sub using carry logic).Mode = 1 → logic path (e.g., bitwise AND/OR/XOR). Verification / Alternative check: Referencing common ALUs (e.g., 74181-style designs) shows a mode input M that selects logic vs arithmetic; function select lines then pick the exact function. Why Other Options Are Wrong: One's-complemented: Complements are specific operations, not the class toggle.Positive/negative: Sign is a consequence of data, not a mode.With/without carry: Carry-in enable is a separate control.Synchronous/asynchronous: Timing style is a design property, not an ALU mode selection. Common Pitfalls: Assuming the mode pin chooses the exact operation; it typically selects the domain, while other lines choose the specific function. Final Answer: Arithmetic or logic

Question 2

Binary adders in digital electronics A standard binary adder (parallel adder built from full-adder stages) is designed to add how many binary numbers simultaneously?

Accepted Answer

Introduction / Context: Binary adders are foundational arithmetic circuits used in ALUs, microcontrollers, and digital signal processors. A parallel binary adder is typically constructed from cascaded full-adder stages to add two multi-bit binary numbers at the same time. This question checks whether you understand how many operands a conventional binary adder handles concurrently. Given Data / Assumptions: A “binary adder” refers to the common ripple-carry or look-ahead adder composed of full-adders. Each full-adder stage accepts bits from two operands and a carry-in. We are not discussing multi-operand compressor trees unless otherwise stated. Concept / Approach: A full-adder takes three 1-bit inputs: A, B, and Cin. The A and B inputs are the two operand bits, while Cin is a carry propagated from the previous (lower significant) stage. Although three inputs exist, only two of them are operand bits; the third is a carry chain signal, not an independent third number. Therefore, a standard parallel adder adds exactly two multi-bit binary numbers at once. Step-by-Step Solution: Recognize full-adder inputs: A, B are operand bits; Cin is carry.Cascading n full-adders forms an n-bit adder for two n-bit operands.Hence, the binary adder adds 2 numbers simultaneously. Verification / Alternative check: Block diagrams of ripple-carry and carry look-ahead adders universally show two operand buses (X and Y) and a single carry-in line, confirming the two-operand design. Why Other Options Are Wrong: 4, 6, 8: These imply multi-operand addition in a single stage, which would require compressor trees (e.g., carry-save adders) or sequential accumulation, not a standard binary adder. Common Pitfalls: Confusing carry-in with a third independent operand. Assuming accumulation over time (adding many numbers sequentially) equates to simultaneous multi-operand addition. Final Answer: 2

Question 3

Half-adders forming a full-adder — do we need any extra gate? True or False: Two half-adders can be combined to implement a full-adder with no additional gates required.

Accepted Answer

Introduction / Context: Half-adders and full-adders are core arithmetic blocks. A well-known construction uses two half-adders to build a full-adder. However, designers must remember the role of the carry path when combining them. This question evaluates whether you know the exact gate requirements for that composite design. Given Data / Assumptions: A half-adder outputs Sum = A XOR B and Carry = A AND B. A full-adder needs Sum = A XOR B XOR Cin and Cout = majority(A, B, Cin). Standard CMOS or TTL logic is assumed. Concept / Approach: To implement a full-adder from two half-adders: First half-adder computes S1 = A XOR B and C1 = A AND B. The second half-adder takes S1 and Cin to produce Sum = S1 XOR Cin and C2 = S1 AND Cin. The final carry-out is Cout = C1 OR C2. Note the need for an OR gate to combine the two carry signals. Step-by-Step Solution: Use Half-Adder 1: S1 = A XOR B; C1 = A AND B.Use Half-Adder 2: Sum = S1 XOR Cin; C2 = S1 AND Cin.Form Cout: Cout = C1 OR C2 → requires an additional OR gate beyond the two half-adders. Verification / Alternative check: Any textbook realization shows the extra OR gate for carry-out. Simulation or truth-table enumeration confirms that without the OR gate, Cout is not correct for all input combinations. Why Other Options Are Wrong: True: Incorrect because at least one extra OR gate is required to produce the full-adder carry-out. Common Pitfalls: Assuming the two half-adders alone are sufficient and forgetting the carry combination. Confusing the internal gates of an integrated “full-adder” IC with a discrete two half-adder construction. Final Answer: False

Question 4

Hexadecimal to decimal conversion What is the decimal (base-10) value of the hexadecimal number E16?

Accepted Answer

Introduction / Context: Hexadecimal (base-16) digits map to decimal values 0–15. Converting single hex digits to decimal is a routine skill used in addressing, color codes, and low-level programming. The digit E in hex corresponds to a specific decimal value. Given Data / Assumptions: Hex digits: 0–9 map to 0–9; A–F map to 10–15. E is the 14th value when counting from zero. Concept / Approach: Since E is a single hex digit, its decimal value is simply the mapping for E. No positional weighting is necessary beyond one digit (i.e., 16^0 = 1). Step-by-Step Solution: Recall mapping: A=10, B=11, C=12, D=13, E=14, F=15.Therefore, E16 = 14 in decimal. Verification / Alternative check: Check a standard hex table or compute using Unicode/ASCII hex conversion guides used in programming references. Why Other Options Are Wrong: 12, 13, 15: Neighboring values for C, D, and F, but not E. Common Pitfalls: Off-by-one errors when counting hex digits. Confusing letter case (e/E) which does not affect numeric value. Final Answer: 14

Question 5

Minimum inputs for a full-adder How many input signals must a full-adder have to perform one-bit addition with carry?

Accepted Answer

Introduction / Context: The full-adder is the standard one-bit arithmetic building block in digital systems. It extends the half-adder by including carry propagation, enabling multi-bit addition via cascading. Recognizing its inputs is essential for correct interfacing and timing analysis. Given Data / Assumptions: Signals involved: operand bit A, operand bit B, and carry-in Cin. Outputs: Sum and carry-out Cout. Concept / Approach: A full-adder must account for two operand bits and an incoming carry from a less significant stage. Therefore it needs exactly three inputs. Any additional inputs would imply extra operands or control not part of the canonical full-adder definition. Step-by-Step Solution: Identify operands: A and B.Account for carry chain: Cin.Count inputs: 3 total. Verification / Alternative check: Standard truth tables for a full-adder show 2^3 = 8 rows, confirming three inputs (A, B, Cin). Why Other Options Are Wrong: 2: That is a half-adder (no carry-in). 4 or 5: Would represent nonstandard or extended adders (e.g., with extra operands or control), not the basic full-adder. Common Pitfalls: Confusing the full-adder with a half-adder. Miscounting Cin as an output rather than an input. Final Answer: 3

Question 6

Key distinction between half-adder and full-adder What is the major functional difference that a full-adder provides compared to a half-adder?

Accepted Answer

Introduction / Context: Half-adders and full-adders both compute binary sums, but only one supports carry propagation, which is essential for multi-bit addition in arithmetic logic units. This question targets your understanding of that essential extension. Given Data / Assumptions: Half-adder inputs: A, B → outputs: Sum, Carry. Full-adder inputs: A, B, Cin → outputs: Sum, Cout. Concept / Approach: The full-adder’s distinguishing feature is the ability to accept a carry-in (Cin) from the previous stage, enabling chaining across multiple bit positions. Without Cin, multi-bit addition cannot propagate carry, which is why half-adders alone are insufficient for parallel addition of multi-bit numbers. Step-by-Step Solution: Identify missing feature in half-adder: no carry-in.Recognize full-adder adds Cin to A and B: Sum = A XOR B XOR Cin.Thus, the major difference is the carry input capability. Verification / Alternative check: Truth tables demonstrate that full-adders cover 8 input combinations (A, B, Cin), whereas half-adders cover 4 combinations (A, B). Why Other Options Are Wrong: “Nothing basically”: Incorrect; the carry input is fundamental. “Handle double-digit numbers”: Number of digits is unrelated; cascading is what matters. “Half adders can handle only single-digit numbers”: Misleading phrasing; limitation is lack of Cin, not “digits.” Common Pitfalls: Assuming two half-adders automatically equal a full-adder without the OR gate for carries. Confusing decimal “digits” with binary bit-widths. Final Answer: Full adders have a carry input capability.

Question 7

Signed number representation — most common method Which signed-binary representation is most commonly used in digital systems for arithmetic?

Accepted Answer

Introduction / Context: Storing negative numbers in binary requires a signed representation. Hardware designers overwhelmingly choose one approach because it simplifies arithmetic and hardware implementation. This question asks you to identify that dominant choice. Given Data / Assumptions: Target: general-purpose CPUs, microcontrollers, DSPs. Requirements: efficient addition/subtraction, unique zero, straightforward overflow behavior. Concept / Approach: 2's-complement provides a single representation for zero, simple subtraction by addition of complements, and the same adder hardware for signed and unsigned arithmetic. 1's-complement has two zeros; sign-magnitude complicates arithmetic with separate sign handling. 10's-complement is for decimal systems, not binary hardware. Step-by-Step Solution: Compare properties: unique zero, simple adder reuse → 2's-complement excels.Note disadvantages in alternatives: two zeros in 1's-complement; sign-magnitude requires extra sign logic.Hence, the most common method is 2's-complement. Verification / Alternative check: ISA specifications (e.g., x86, ARM, RISC-V) and compiler assumptions confirm 2's-complement as the de facto standard for signed integers. Why Other Options Are Wrong: 1's-complement: dual zeros and end-around carry complexity. 10's-complement: decimal-specific, not binary hardware. Sign-magnitude: inefficient arithmetic and two sign cases. Common Pitfalls: Confusing the 2's-complement operation with bitwise NOT (which is 1's-complement). Forgetting that range is asymmetric (one extra negative value) in 2's-complement. Final Answer: 2's-complement system.

Question 8

2's-complement subtraction by addition When subtracting using the 2's-complement method, which operand is complemented before performing the addition?

Accepted Answer

Introduction / Context: Digital systems perform subtraction by reusing the same adder hardware used for addition. The trick is to convert subtraction into addition using 2's-complement arithmetic. This question asks you to recall which operand is complemented in that process. Given Data / Assumptions: We want A - B using 2's-complement arithmetic. 2's-complement of a number X is formed by inverting all bits (1's-complement) and then adding 1. Concept / Approach: Compute A - B as A + (2's-complement of B). The minuend A remains unchanged, and only the subtrahend B is transformed. Addition is then performed; any final carry out is discarded in fixed-width arithmetic, leaving the correct signed result. Step-by-Step Solution: Form B' = 2's-complement(B) = NOT(B) + 1.Compute S = A + B' using the standard adder.Interpret result as signed 2's-complement value; ignore carry-out if present. Verification / Alternative check: Example: 7 - 5. In 4-bit 2's-complement, 5 → 0101, B' = 1011. Add 0111 + 1011 = 1 0010; discard carry, result 0010 = 2, which is correct. Why Other Options Are Wrong: Complementing both operands or the minuend changes the intended operation and breaks the identity A - B = A + (2's-complement of B). Leaving both unchanged would simply compute A + B, not subtraction. Common Pitfalls: Forgetting to add 1 after inversion when forming 2's-complement. Misinterpreting carry-out handling in fixed-width arithmetic. Final Answer: the minuend is left in its original form and the subtrahend is changed to its 2's-complement.

Question 9

What does a full-adder add in one operation? Choose the statement that correctly describes the inputs combined by a full-adder cell.

Accepted Answer

Introduction / Context: The full-adder is the building block of multi-bit adders. Understanding exactly what each cell adds clarifies how n-bit adders are constructed by cascading these cells along a carry chain. Given Data / Assumptions: A full-adder has inputs A, B (operand bits) and Cin (carry-in). Outputs are Sum and Cout (carry-out). Concept / Approach: Each full-adder processes a single bit from each of two operands plus the incoming carry from the previous lower-order bit. It does not directly add multi-bit numbers; instead, many full-adders in parallel handle different bit positions to realize multi-bit addition. Step-by-Step Solution: Identify operands: A and B are single-bit inputs.Include carry chain: Cin is the third input.Therefore, a full-adder adds two single bits and one carry bit at a time. Verification / Alternative check: Truth tables and gate-level schematics of a full-adder confirm three inputs and two outputs, with Cout feeding the next stage. Why Other Options Are Wrong: Two 2-bit or two 4-bit numbers: These require multiple full-adders arranged in parallel, not a single cell. Two 2-bit numbers and one carry bit: Same issue; implies a multi-bit adder, not a single full-adder cell. Common Pitfalls: Assuming the presence of multi-bit buses per cell; in reality each cell handles one bit position. Overlooking that Cin is an input, not an output. Final Answer: two single bits and one carry bit

Question 10

Hex arithmetic — add three independent hexadecimal pairs Add the following hex numbers as three separate sums: (3C + 25), (14 + 28), and (3B + DC). Choose the triple that shows all three results in order.

Accepted Answer

Introduction / Context: Hexadecimal addition is a routine digital-design skill used in addressing, checksums, and low-level debugging. This problem asks you to compute three independent hex sums and present the answers in order, demonstrating correct base-16 arithmetic and carry handling. Given Data / Assumptions: Sums to compute: (3C + 25), (14 + 28), (3B + DC). All values are hexadecimal (base 16). Show each result in hex; the last result may exceed 2 hex digits if a carry propagates. Concept / Approach: Add digit by digit in base 16, where A=10, B=11, C=12, D=13, E=14, F=15. When a nibble sum is 16 or more, write the low nibble and carry 1 to the next higher nibble. Convert to decimal only if it helps verify reasonableness, then convert back to hex as needed. Step-by-Step Solution: 3C + 25 = (0x3C = 60) + (0x25 = 37) = 97 decimal = 0x61 → result 6114 + 28 = (0x14 = 20) + (0x28 = 40) = 60 decimal = 0x3C → result 3C3B + DC = (0x3B = 59) + (0xDC = 220) = 279 decimal = 0x117 → result 117 Verification / Alternative check: Quick nibble check: 0x3C + 0x25 → C + 5 = 17 (write 7, carry 1), 3 + 2 + 1 = 6 → 0x61. Similarly, 0x14 + 0x28 = 0x3C. For 0x3B + 0xDC, lower nibble B + C = 11 + 12 = 23 → write 7 carry 1; upper nibble 3 + D + 1 = 3 + 13 + 1 = 17 → write 1 carry 1 to hundreds → 0x117. Why Other Options Are Wrong: 60 3C 116 and 62 3C 118: off by one on each sum due to carry mistakes. 61 3D 117: middle sum should be 3C, not 3D. 5F 41 0F5: multiple digit errors and mis-handled carries. Common Pitfalls: Treating hex digits as decimal when carrying. Forgetting that 0xF + 0x1 = 0x10 produces a new hex digit. Final Answer: 61 3C 117

Question 11

Binary multiplication — compute three 4-bit × 4-bit products Multiply these binary pairs independently and write each 8-bit product in order: (1010 × 0011), (1011 × 0111), (1001 × 1010).

Accepted Answer

Introduction / Context: Binary multiplication underpins arithmetic units in processors and programmable logic. Here you multiply three 4-bit operands by three 4-bit operands and present each 8-bit product, testing understanding of place value and partial products in base 2. Given Data / Assumptions: P1: 1010 × 0011 P2: 1011 × 0111 P3: 1001 × 1010 Unsigned binary; output each product as 8 bits with a space every 4 bits for readability. Concept / Approach: Convert to decimal to verify, or perform shift-and-add: multiplying by 2^k is a left shift by k. Sum partial products and limit to 8 bits for 4×4. Finally, sanity-check by converting back to decimal. Step-by-Step Solution: P1: 1010 (10) × 0011 (3) = 30 → 0001 1110P2: 1011 (11) × 0111 (7) = 77 → 0100 1101P3: 1001 (9) × 1010 (10) = 90 → 0101 1010 Verification / Alternative check: Shift-add for P1: 1010 × (0011) = 1010 + (1010 << 1) = 1010 + 10100 = 11110 → zero-extend to 0001 1110. Similar checks confirm P2 = 0x4D, P3 = 0x5A. Why Other Options Are Wrong: Option a: last group 0101 1011 = 91, not 90. Option b: second group 0100 1100 = 76, not 77. Option d: first group 0001 1101 = 29, not 30. Option e: multiple groups deviate from correct decimal equivalents. Common Pitfalls: Forgetting that binary multiplication by 2 is a left shift. Dropping carries when summing partial products. Final Answer: 0001 1110 0100 1101 0101 1010

Question 12

BCD conversion and addition — add 275 and 965 in BCD Convert the decimal numbers 275 and 965 to BCD, perform BCD addition, and select the BCD groups that represent the final sum (thousands to ones).

Accepted Answer

Introduction / Context: Binary-coded decimal (BCD) represents each decimal digit with its own 4-bit code, which is common in digital displays and decimal arithmetic units. This task checks your ability to encode, add, and recognize the BCD result. Given Data / Assumptions: Numbers: 275 and 965 (decimal). BCD digit mapping: 0→0000, 1→0001, …, 9→1001. Use BCD addition with decimal correction when a digit sum exceeds 9. Concept / Approach: Add the decimal numbers first to know the expected result, then encode that result into BCD. Alternatively, convert each operand to BCD, add digit-wise, and apply a +6 correction (0110) to any digit sum greater than 9 to restore valid BCD and propagate carries. Step-by-Step Solution: Compute: 275 + 965 = 1240 (decimal).Encode each digit: 1→0001, 2→0010, 4→0100, 0→0000.Concatenate thousands to ones: 0001 0010 0100 0000. Verification / Alternative check: Digit-wise BCD add: 5 + 5 = 10 → write 0, carry 1; 7 + 6 + 1 = 14 → write 4, carry 1; 2 + 9 + 1 = 12 → write 2, carry 1 to thousands → 1. Encoded result is identical to the direct conversion of 1240. Why Other Options Are Wrong: Options a, b: not valid BCD for 1240; include invalid digit codes or wrong order. Option d: 2 3 4 0 (2340), not 1240. Option e: 1 2 3 8 (1238), not 1240. Common Pitfalls: Treating 1240 as a binary number rather than BCD groups. Forgetting the +6 correction in BCD digit sums above 9. Final Answer: 0001 0010 0100 0000

Question 13

Digital adders — identifying the two basic adder circuit types In digital electronics, what are the two fundamental adder circuits used to build arithmetic units?

Accepted Answer

Introduction / Context: Binary addition is the core of ALUs. Designers combine simple adder primitives to create multi-bit adders with or without carry look-ahead. Recognizing the two building blocks is essential for understanding ripple-carry and advanced adder topologies. Given Data / Assumptions: A “half-adder” produces Sum and Carry from two input bits. A “full-adder” adds two input bits plus a carry-in and generates Sum and Carry-out. Multi-bit adders cascade full-adders and, optionally, a single half-adder for the least significant stage if no carry-in is required. Concept / Approach: The half-adder implements Sum = A ⊕ B and Carry = A · B. The full-adder extends this with the carry-in: Sum = A ⊕ B ⊕ Cin, Cout = (A · B) + (Cin · (A ⊕ B)). These blocks can be chained to construct n-bit adders and further optimized with carry-lookahead or carry-skip logic. Step-by-Step Solution: Identify primitive adders used universally in texts and ICs (e.g., 7483).Eliminate choices that are categories or properties rather than circuits.Select “half-adder and full-adder.” Verification / Alternative check: Standard logic design curricula and data books define only these two basic adder cells; all other multi-bit adder designs are composed from them with additional acceleration logic. Why Other Options Are Wrong: Sum and carry: outputs, not circuit types. Asynchronous/synchronous: timing categories, not adders. One-/two’s-complement: number representations, not circuits. Parallel/serial adders: system-level architectures built from the basic cells. Common Pitfalls: Confusing output names with circuit names. Assuming “serial adder” is a primitive rather than an architectural use. Final Answer: half-adder and full-adder

Question 14

Design reuse — before using a macrofunction in a PLD/FPGA project What is the first essential thing you need before instantiating and integrating a macrofunction (prebuilt IP block or library function) in your design?

Accepted Answer

Introduction / Context: Macrofunctions (or IP blocks) are pre-verified logic functions used in CPLDs, FPGAs, and EDA flows. Successful reuse depends on understanding interfaces, timing, and configuration. This question focuses on the most critical prerequisite for correct integration. Given Data / Assumptions: You have access to a vendor/library macrofunction. It exposes parameters, timing, clocking, and I/O ports. You must instantiate it correctly in HDL or a schematic. Concept / Approach: Good documentation (datasheets, user guides, timing diagrams, constraint templates) tells you how to wire clocks, resets, enables, and data paths; what parameter values are valid; and what timing/throughput to expect. Without it, even experienced designers risk misconnection, incorrect constraints, or violating timing assumptions. Step-by-Step Solution: Identify the true dependency for correctness: knowledge of interface and timing → documentation.Note that project complexity or staff seniority does not replace required specs.Conclude that “Good documentation” is first and foremost. Verification / Alternative check: Industry best practices require consulting IP release notes and integration guides before coding. Tool-generated examples and constraints are part of the documentation set. Why Other Options Are Wrong: Complicated project: not a prerequisite. Experienced engineer / HDL experience: helpful, but useless without the necessary specs. Custom floorplan: sometimes needed later, not the first requirement. Common Pitfalls: Instantiating IP without checking clock domain requirements and reset polarity. Ignoring latency and valid/ready handshakes described in the docs. Final Answer: Good documentation

Question 15

Two’s-complement subtraction — 43 − 15 using 6-bit representation When subtracting decimal 15 from 43 in binary using two’s complement (6-bit width), which two’s-complement value must be added to 43?

Accepted Answer

Introduction / Context: Binary subtraction is commonly performed by adding the two’s-complement of the subtrahend. This problem tests whether you can form the correct two’s-complement for a given decimal number using a fixed bit width and apply it to a subtraction example. Given Data / Assumptions: Compute 43 − 15 using 6 bits. Two’s-complement formation: invert bits (one’s-complement) then add 1. 15 in 6-bit binary is 00 1111. Concept / Approach: To subtract B from A, compute A + (two’s-complement of B). The two’s-complement of B is formed by inverting all bits of B (with respect to the chosen width) and adding 1. Ensure the correct width to avoid sign or overflow mistakes. Step-by-Step Solution: Represent 15 in 6 bits: 001111.One’s-complement: 110000.Two’s-complement: 110000 + 1 = 110001.Add to 43 (101011) to verify: 101011 + 110001 = 1 011100; discard carry → 011100 (28 decimal), which equals 43 − 15. Verification / Alternative check: Decimal check: 43 − 15 = 28. Binary result 011100 is 28, confirming that 110001 was the correct two’s-complement to add. Why Other Options Are Wrong: 110000: this is only the one’s-complement; you must add 1. 101011 and 011100: these are 43 and 28 respectively, not the required complement. 001111: original +15 rather than its negative. Common Pitfalls: Forgetting to fix the bit width before forming complements. Failing to add 1 after inversion. Final Answer: 110001

Question 16

ALU control — meaning of selector inputs In a typical arithmetic/logic unit (ALU), what do the selector inputs determine during operation?

Accepted Answer

Introduction / Context: An ALU performs many operations (add, subtract, AND, OR, XOR, shifts). Control lines, often called selector inputs, choose which operation is applied to the input operands. Understanding this is foundational for CPU datapaths and programmable logic blocks. Given Data / Assumptions: An ALU has data inputs (operands), control/selector inputs, and status outputs (carry, zero, overflow). Clocking is handled elsewhere (e.g., in a register stage), not by the ALU function selector. Concept / Approach: The selector inputs are decoded inside the ALU to route operands through the appropriate combinational network (adder, boolean logic, shifter). Different codes map to different functions. Timing (clock) and device selection are external system concerns, not chosen by these lines. Step-by-Step Solution: Identify what varies at the ALU per instruction: the function being executed.Map selector codes to operations (e.g., 000 = ADD, 001 = SUB, 010 = AND, 011 = OR, etc.).Therefore, selector inputs determine the arithmetic or logic function. Verification / Alternative check: Consult any standard 74xx ALU (e.g., 74181) or FPGA soft-ALU: the select pins choose the operation while separate enables or registers handle timing and chip-select. Why Other Options Are Wrong: IC selection and clock frequency are system-level signals, not ALU function selects. Data word selection is performed by multiplexers, not the ALU's function selector. Supply voltage is fixed by design, not chosen by control lines. Common Pitfalls: Confusing ALU select codes with opcode decoding stages that also handle register addressing. Final Answer: arithmetic or logic function

Question 17

One-bit binary subtraction — counting the distinct cases For a single-bit subtraction cell (with possible borrow), how many basic binary subtraction operations (input cases) exist?

Accepted Answer

Introduction / Context: Understanding the truth table of a 1-bit subtractor (with or without borrow) is key to designing ripple-borrow subtractors and two’s-complement adders/subtractors. Counting the distinct input cases helps define the required logic. Given Data / Assumptions: Consider basic A − B for one bit, ignoring an incoming borrow to keep the canonical “basic” set. Binary digits A and B can each be 0 or 1. Concept / Approach: There are two inputs (A, B) with 2 states each, so total combinations = 2^2 = 4. These correspond to: 0 − 0, 0 − 1, 1 − 0, and 1 − 1. Each case has a defined difference bit and potentially a borrow out. If a borrow-in is included, the truth table doubles again to 8 cases (2^3), but the term “basic binary subtraction operations” typically refers to A and B only. Step-by-Step Solution: Enumerate pairs: (0,0), (0,1), (1,0), (1,1) → 4 basic cases.Associate outcomes: differences 0, 1, 1, 0 with appropriate borrows for the two cases that require it. Verification / Alternative check: Compare with the half-subtractor definition which explicitly has a 2-input, 2-output truth table covering four input rows. Why Other Options Are Wrong: 3, 2, or 1: undercount the combinations. 8: corresponds to including an extra borrow-in input (full subtractor), not the basic case. Common Pitfalls: Accidentally mixing “half-subtractor” (no borrow-in) with “full subtractor” (with borrow-in). Final Answer: 4

Question 18

Building wider adders — cascading 4-bit adders to form a 16-bit adder When constructing a 16-bit adder from 4-bit adder ICs, what is required?

Accepted Answer

Introduction / Context: Multi-bit addition is often implemented by cascading smaller adder blocks (e.g., 4-bit 74xx adders). Understanding how many ICs are needed and how to connect their carry signals is fundamental to designing arithmetic datapaths. Given Data / Assumptions: Target width: 16 bits. Available building block: a 4-bit adder with carry-in (Cin) and carry-out (Cout). Ripple-carry architecture unless a separate carry-lookahead is used. Concept / Approach: Divide the 16-bit vectors into four 4-bit slices: bits [3:0], [7:4], [11:8], [15:12]. Each slice uses one 4-bit adder. Chain the carry: Cout from the less significant slice feeds Cin of the next slice. Optionally tie Cin of the least significant slice to 0 for simple addition or to 1 for add-with-carry (increment). Step-by-Step Solution: Number of slices = 16 / 4 = 4 → four 4-bit adders required.Connect carry chain: Cout(LS nibble) → Cin(next nibble) → … → Cout(MS nibble).Tie Cin(LS nibble) per required function. Verification / Alternative check: This is the canonical ripple-carry adder construction and matches vendor datasheets and textbook examples. Carry-lookahead units can accelerate the chain but still maintain the same basic slice count and carry connectivity. Why Other Options Are Wrong: 16 adders: confuses bit count with IC count. 4 adders only: incomplete—omits the crucial carry-chain requirement. Carry chain only: incomplete—must also state four adders. 8 adders, no carry chain: both incorrect. Common Pitfalls: Forgetting to propagate carry, yielding wrong sums at higher slices. Mixing slice order so that carries run backward. Final Answer: requires 4 adders and the connection of the carry out of the less significant adder to the carry-in of the next significant adder.

Question 19

In binary-coded decimal (BCD) arithmetic used in digital electronics and calculators, which single operation is the most fundamental (i.e., used most often and forms the basis for other operations such as subtraction via complements and multi-digit …

Accepted Answer

Introduction / Context: BCD (binary-coded decimal) arithmetic is widely used in financial calculators, display drivers, and embedded systems that must handle decimal digits accurately. The question tests whether you know which operation underpins most BCD processing and serves as the building block for other arithmetic procedures. Given Data / Assumptions: BCD encodes each decimal digit independently using 4 bits (0000 to 1001 for 0–9). We consider basic arithmetic on BCD-encoded multi-digit numbers. Standard digital design practice: complex operations are composed from simpler primitives. Concept / Approach: In BCD arithmetic, addition is the core primitive. Subtraction is typically performed as addition of a complement (ten's complement in decimal or BCD-corrected nine's complement plus 1). Multi-digit multiplication reduces to repeated additions of shifted partial products with BCD correction. Division uses repeated subtraction, which again relies on addition/comparison hardware and correction logic. Therefore, addition is the central operation around which BCD ALUs are designed. Step-by-Step Solution: 1) Identify the operation most reused by others: addition is used directly and indirectly (via complements).2) Note that subtraction equals addition of a complement, implemented with adder hardware plus correction.3) Recognize that multiplication is repeated addition of partial products, digit by digit, with BCD correction.4) Division employs repeated subtraction (hence addition of complements) and comparisons. Verification / Alternative check: Inspect typical BCD ALU datapaths: the largest logic block is the BCD adder with correction (add 6 when a nibble exceeds 9 or when a carry is produced). Other arithmetic units reuse this block. Why Other Options Are Wrong: Subtraction: implemented using addition of complements.Multiplication: built from repeated additions with shifts.Division: based on repeated subtraction/comparison, again leveraging addition hardware.Iterative shifting: supports arithmetic but is not the arithmetic operation itself. Common Pitfalls: Assuming subtraction is separate in hardware; in many BCD ALUs it reuses the adder. Also, forgetting the BCD correction step (adding 6 when a nibble exceeds 1001) can lead to wrong decimal digits. Final Answer: addition

Question 20

Add in pure binary: 26 + 27. Write the final sum in binary without leading text.

Accepted Answer

Introduction / Context: Binary addition is foundational for digital logic and computer arithmetic. This problem asks you to convert two decimal values to binary, perform the addition, and express the sum in binary form. Given Data / Assumptions: Operands: 26 and 27 (decimal, unsigned). We need the exact binary sum. No overflow concerns for this small sum. Concept / Approach: Convert each decimal number to binary, then add the bit patterns using standard binary addition rules (0+0=0, 0+1=1, 1+1=0 with carry 1). Convert back to decimal as a check. Step-by-Step Solution: 1) Convert 26 to binary: 26 = 16 + 8 + 2 = 11010.2) Convert 27 to binary: 27 = 16 + 8 + 2 + 1 = 11011.3) Add: 11010 + 11011 = 110101.4) Check in decimal: 26 + 27 = 53; 110101 (binary) = 32 + 16 + 4 + 1 = 53. Verified. Verification / Alternative check: Use positional weights or quickly re-add in decimal and reconvert: 53 → 32 + 16 + 4 + 1 → 110101. Matches the computed binary sum. Why Other Options Are Wrong: 111010 (58), 110110 (54), 101011 (43), 100101 (37): all represent incorrect decimal totals for 26 + 27. Common Pitfalls: Misplacing carries during addition or mis-conversion between decimal and binary. Writing unequal bit lengths without proper alignment can also cause errors. Final Answer: 110101

Digital Arithmetic Operations and Circuits Questions