Question 1

Two's-complement calculation: Find the 2's-complement of 00001111 (8-bit representation).

Accepted Answer

Introduction / Context: Two's-complement is the dominant signed number encoding in digital systems. It is formed by inverting all bits (one's-complement) and then adding 1 to the least significant bit. Given Data / Assumptions: Original byte: 00001111 (decimal 15). We want its 2's-complement in 8 bits. Concept / Approach: 2's-complement(X) = (~X) + 1. For 00001111: one's-complement is 11110000; adding 1 yields 11110001. Step-by-Step Solution: Compute one's-complement: 00001111 → 11110000.Add 1: 11110000 + 00000001 = 11110001.Confirm bit width: keep 8 bits. Verification / Alternative check: Adding the number and its 2's-complement gives 00000000 with a carry out, confirming correctness. Why Other Options Are Wrong: 11111111: That is 2's-complement of 00000001.11110000: Only one's-complement; missing +1.11110111: Incorrect increment.00010000: Not related to the required operation. Common Pitfalls: Stopping at inversion without adding 1, or changing bit width inadvertently. Final Answer: 11110001

Question 2

Capabilities of a 4-bit adder IC: Which operation(s) can a standard 4-bit binary adder perform without additional gating logic?

Accepted Answer

Introduction / Context: A 4-bit adder IC (e.g., 74HC283/74LS283) provides parallel addition of two 4-bit operands with Cin/Cout for cascading. Other arithmetic/logic functions often require external gating or dedicated ALU chips. Given Data / Assumptions: Device: standard 4-bit adder, not a full ALU. Inputs: A[3:0], B[3:0], Cin; Outputs: S[3:0], Cout. Concept / Approach: Plain addition is native. Subtraction can be realized in a system by inverting B and setting Cin=1 (two's-complement technique), but that requires extra inversion hardware; the bare adder alone does not implement subtraction or AND by itself. Therefore, the only operation directly supported by the chip without external gating is addition. Step-by-Step Solution: Identify native function from pinout/equations: Sum = A xor B xor Cin.Non-native functions (subtraction/AND) need extra logic.Hence, direct capability = addition only. Verification / Alternative check: Datasheets name the part a “binary adder”; subtraction examples always show complemented inputs and Cin=1 using extra gates. Why Other Options Are Wrong: Subtraction: Requires complementing B and setting Cin=1.Logical AND: Requires gate logic, not a sum circuit.All of the above / parity: Not provided by a plain adder. Common Pitfalls: Assuming ALU capabilities from an adder part number. Final Answer: addition

Question 3

1-bit binary subtraction (borrow logic): Compute 1 − 1 and report the difference and borrow.

Accepted Answer

Introduction / Context: Single-bit subtraction defines core behavior for multi-bit subtractors. When the minuend bit equals the subtrahend bit and no prior borrow exists, the result is straightforward. Given Data / Assumptions: Subtracting a = 1 by b = 1. No incoming borrow (borrow_in = 0). Concept / Approach: For one bit: difference = a xor b xor borrow_in; borrow_out = (~a & b) | ((~a | b) & borrow_in). With a=b=1 and borrow_in=0, difference=0 and borrow_out=0. Step-by-Step Solution: Compute difference: 1 xor 1 xor 0 = 0.Compute borrow: (~1 & 1) | ((~1 | 1) & 0) = (0 & 1) | (1 & 0) = 0.Report: difference 0, borrow 0. Verification / Alternative check: Decimal view: 1 − 1 = 0 with no need to borrow. Why Other Options Are Wrong: Any nonzero difference/borrow contradicts the computation. Common Pitfalls: Forgetting to specify borrow_in assumptions. Final Answer: difference = 0 borrow = 0

Question 4

2-bit vector operation (recovered intent = addition): Given 2-bit unsigned vectors [A] = 10 and [B] = 01 (A is MSB), compute [A] + [B].

Accepted Answer

Introduction / Context: The original stem omitted the operator; by Recovery-First we adopt the standard teaching example aligned with nearby items: 2-bit vector addition. Treat [A]=10 (binary 2) and [B]=01 (binary 1) as unsigned and add them. Given Data / Assumptions: Vectors are 2 bits wide, A is MSB. Unsigned addition; no saturation. Result reported as a 2-bit vector (no overflow here). Concept / Approach: 2 + 1 = 3. In binary, 3 is 11, which fits in 2 bits; no extra carry beyond the 2-bit width is generated. Step-by-Step Solution: LSB: 0 + 1 = 1, carry 0.MSB: 1 + 0 + carry 0 = 1.Concatenate → [11]. Verification / Alternative check: Decimal check: 2 + 1 = 3 → binary 11. Why Other Options Are Wrong: [00]/00: Sum is not zero.11 (without brackets) lacks the vector format; still the same value but formatting inconsistent.[10] with carry: Incorrect; no carry occurs. Common Pitfalls: Misreading the MSB/LSB order. Final Answer: [11]

Question 5

1-bit binary addition (sum and carry): Compute 1 + 1 and report the sum and carry.

Accepted Answer

Introduction / Context: Single-bit addition defines the core behavior of ripple and CLA adders. Adding two ones produces a sum bit and a carry to the next stage. Given Data / Assumptions: a = 1, b = 1, carry_in = 0. Standard full-adder equations. Concept / Approach: Sum = a xor b xor carry_in; Carry_out = majority(a, b, carry_in). With a=b=1 and carry_in=0, Sum=0 and Carry_out=1. Step-by-Step Solution: Compute sum: 1 xor 1 xor 0 = 0.Compute carry: majority(1,1,0) = 1.Report (sum, carry) = (0, 1). Verification / Alternative check: Truth table of a half adder shows 1+1 → sum 0, carry 1. Why Other Options Are Wrong: Any combination other than sum 0, carry 1 contradicts equations. Common Pitfalls: Forgetting to include the carry signal when moving to the next bit. Final Answer: sum = 0 carry = 1

Question 6

Hex subtraction: Compute FC48 − AB91 (hexadecimal). Choose the correct hex result.

Accepted Answer

Introduction / Context: Hex arithmetic is common in low-level debugging and digital design. Subtracting two 16-bit hex values can be done by column subtraction with borrows or by converting to integers and back. Given Data / Assumptions: Operands: FC48 and AB91 (hex). Unsigned subtraction. Concept / Approach: Either convert to decimal and subtract, or perform hex column subtraction: (FC48) − (AB91) = 50B7. Step-by-Step Solution: 8 − 1 = 7.4 − 9 → borrow: (4+16) − 9 = 11 = B; borrow 1.(C=12) − (B=11) with prior borrow cleared: 12 − 11 = 1, but remember the previous borrow was already applied in the lower nibble; recompute carefully across bytes to confirm final: 0xFC48 − 0xAB91 = 0x50B7.F − A = 5 (after handling intermediate borrows). Verification / Alternative check: Integer check: 0xFC48 (64584) − 0xAB91 (43921) = 20663 = 0x50B7. Why Other Options Are Wrong: 5B77/5267/5077/4FB7: Do not equal the computed difference. Common Pitfalls: Dropping a borrow between nibbles or mixing decimal and hex digits. Final Answer: 50B7

Question 7

Two's-complement subtraction rule: When subtracting 6 from 9 using a 2's-complement adder, the ________ is 2's-complemented before the addition.

Accepted Answer

Introduction / Context: Digital subtractors typically reuse adder hardware by representing subtraction A − B as A + 2's-complement(B). This technique works for any word size and unifies the implementation of add and subtract. Given Data / Assumptions: We wish to compute 9 − 6. Arithmetic is performed using a 2's-complement adder. Concept / Approach: Form the 2's-complement of the subtrahend (6) and add it to the minuend (9). Equivalently, invert the bits of 6 and add 1, then add to 9, propagating carries as usual. Step-by-Step Solution: Identify minuend A = 9 and subtrahend B = 6.Compute B_tc = two's-complement(B) = (~B) + 1.Add: A + B_tc; ignore end carry in fixed-width arithmetic. Verification / Alternative check: Numerically, 9 + (−6) = 3, matching the intended subtraction. Why Other Options Are Wrong: Multiplier/two/result/nine: Not the subtrahend; subtraction requires complementing B, not A. Common Pitfalls: Confusing one's-complement (~B) with two's-complement (~B + 1). Final Answer: six

Question 8

VHDL packages – what do they primarily collect and expose so multiple entities/architectures in a design can share common resources (types, subprograms, constants, component declarations)?

Accepted Answer

Introduction / Context: In VHDL-based digital design, reusability and clear separation of concerns are vital. A key mechanism enabling this modularity is the package, which collects items that need to be visible across multiple entities and architectures within a project or library. Understanding exactly what belongs in a package prevents name collisions, reduces duplication, and makes testbenches and implementations consistent. Given Data / Assumptions: Designs may contain many entities/architectures spread across files. Multiple components, types, constants, and subprograms must be shared. We want a single authoritative place for such shared items. Concept / Approach: A VHDL package aggregates declarations: type and subtype declarations, constants, signals (rare in practice), records, arrays, function/procedure headers and bodies (if in a package body), and component declarations. These declarations can then be made visible by using a use clause (for example, use work.my_pkg.all;). Placing declarations in one package avoids copying definitions across multiple files and ensures that changes propagate predictably. Step-by-Step Solution: 1) Identify what must be reused: types, constants, components, subprograms.2) Put the declarations into a package (and, if needed, bodies into a package body).3) Compile the package into a library (often work).4) Make items visible with use clauses where required. Verification / Alternative check: Industrial and academic code bases standardize on packages (for example, numeric_std) that provide shared declarations such as numeric types and overloaded arithmetic functions, confirming the role of packages as holders of declarations rather than concrete instances or timing data. Why Other Options Are Wrong: “vectors” are specific type instances; packages hold the declaration of a vector type, not a particular signal vector. “instances” are created in architectures via component/entity instantiation, not stored in packages. “timing models” and “configuration bits” are tool- or device-specific artifacts, not VHDL package contents. Common Pitfalls: Confusing declarations with objects (signals/variables). Packages typically hold declarations, while actual objects live in architectures or blocks. Another pitfall is scattering type definitions across many files, causing maintenance issues. Final Answer: declarations

Question 9

Two’s-complement arithmetic – for arithmetic negation of a signed binary value, which operation should be applied?

Accepted Answer

Introduction / Context: Modern digital systems represent signed integers using the two’s-complement scheme because it unifies addition and subtraction in one adder and avoids separate negative-zero encodings. Knowing how to produce the arithmetic negative of a value is essential for ALU design, HDL coding, and low-level debugging. Given Data / Assumptions: Signed integers are encoded in two’s complement with a fixed word width. Arithmetic negation means producing −X from X. No saturation or overflow handling changes the basic mechanism. Concept / Approach: In two’s-complement arithmetic, arithmetic negation is achieved by computing the two’s complement of the bit pattern: NOT(X) + 1. This yields the unique encoding of −X for every nonzero X and maps 0 to 0. The adder used for addition can also produce subtraction by inverting the subtrahend and adding 1, exploiting exactly this property. Step-by-Step Solution: 1) Start with a signed value X in two’s complement.2) Invert all bits: X_inv = NOT(X).3) Add 1: X_neg = X_inv + 1.4) The result encodes −X in the same word width. Verification / Alternative check: Example (8-bit): X = 00010110 (22). Invert → 11101001, add 1 → 11101010 = −22. Adding X + (−X) yields 00000000 with a discarded carry out, confirming the identity. Why Other Options Are Wrong: “1’s-complement” is a bitwise NOT (forms negative only if followed by +1); alone it leaves a negative-zero issue and is not standard for arithmetic negation. “sign inversion only” (flip MSB) breaks magnitude and is not a valid encoding. “surrogate inversion” and “bit rotate right” are unrelated to arithmetic negation. Common Pitfalls: Forgetting to add 1 after bit inversion, or misinterpreting overflow flags when negating edge cases (e.g., the most negative number, where |min| exceeds |max| in fixed width). Final Answer: 2's-complement

Question 10

Two’s-complement subtraction – which core operation does the hardware actually perform to realize A − B?

Accepted Answer

Introduction / Context: Efficient ALU design avoids separate subtractors by leveraging two’s-complement properties. Subtraction is “free” once addition is available, which simplifies datapaths and timing closure. Understanding this equivalence helps when writing synthesizable HDL and when reading synthesis reports. Given Data / Assumptions: Operands A and B are fixed-width two’s-complement numbers. We want A − B. We can control inversion of B and the initial carry-in of an adder. Concept / Approach: Compute A − B as A + (NOT(B) + 1). The adder accepts B after bitwise inversion while the carry-in is preset to 1, effectively adding the two’s complement of B. The same ripple-carry or carry-lookahead adder thus performs both addition and subtraction, reducing hardware. Step-by-Step Solution: 1) Invert B: B_inv = NOT(B).2) Preset Cin = 1 to add the +1 part of two’s complement.3) Add: Sum = A + B_inv + Cin.4) Interpret result and flags (carry/overflow) per signed/unsigned rules. Verification / Alternative check: Example: 7 − 5 (4-bit). A=0111, B=0101. Invert B→1010; add with Cin=1: 0111 + 1010 + 1 = 1 0000 → 0000 with carry out; because of fixed width, also compute directly with two’s complement of B (1011) to get 0010 = 2, consistent when steps are tracked correctly. The key is that the hardware path is addition with controlled inversion and carry-in. Why Other Options Are Wrong: Dedicated borrow subtractors are unnecessary in two’s complement. Multiplication or division are unrelated. Lookup tables are not how arithmetic is generally synthesized in standard ALUs. Common Pitfalls: Misreading the carry and overflow flags between signed and unsigned modes; forgetting to preset Cin; or accidentally double-adding the +1. Final Answer: addition

Question 11

VHDL architecture structure – what appears first to introduce the variable signals, component declarations, and other items used between BEGIN and END?

Accepted Answer

Introduction / Context: A VHDL architecture defines how an entity behaves. Inside an architecture, there is a clear organization: a declarative region followed by the concurrent statements between BEGIN and END. Recognizing what properly belongs in the declarative part is essential for clean, synthesizable code and comprehensible testbenches. Given Data / Assumptions: An architecture is associated with an entity. Items used in concurrent statements (signals, component declarations, constants, type declarations, subprograms) must be introduced first. Standard coding style places these items in the architecture’s declarative region. Concept / Approach: The architecture begins with a declarations section (the declarative part). There, you declare signals, constants, types/subtypes, component declarations (unless direct entity instantiation is used), and subprograms (or reference them via packages). After the keyword begin, concurrent statements (signal assignments, component/entity instantiations, generate statements) follow and may reference anything declared earlier. Step-by-Step Solution: 1) Write architecture header: architecture rtl of my_entity is.2) Provide declarations (signals, types, constants, components, subprograms).3) Start concurrent region with begin.4) End with end architecture; referencing earlier declarations as needed. Verification / Alternative check: Any basic VHDL reference or IEEE standard shows the grammar: architecture_declarative_part precedes architecture_statement_part. Real-world code (for example, FIFO controllers) places signal and component declarations before begin, validating the rule. Why Other Options Are Wrong: “type keyword only” and “vectors list” are subsets of declarations; the architecture needs a general declarative region, not a single kind of item. “functions only” is too narrow. “library use clauses only” typically appear earlier at file scope, not inside the architecture declarative section exclusively. Common Pitfalls: Declaring items after begin (illegal), or scattering declarations in packages unnecessarily when they are local to the architecture. Keep local declarations local for clarity. Final Answer: declarations

Digital Arithmetic Operations and Circuits Questions