In integrated-circuit technologies, which device class historically dominated large-scale integration (LSI), and which class is preferred where the lowest power consumption is required?

Introduction / Context:
Different MOS logic families exhibit distinct tradeoffs in speed, density, and power. Historically, NMOS processes led the LSI era due to speed and ease of fabrication, while CMOS later became dominant where static power and energy are critical, and ultimately became mainstream for nearly all VLSI because of superior power efficiency. The question probes recognition of these characteristics.

Given Data / Assumptions:

• Focus on historical LSI dominance and low power preference.
• Device families: PMOS, NMOS, CMOS.
• Comparisons consider static and dynamic power, device density, and performance.

Concept / Approach:

NMOS logic typically offered faster devices than PMOS and was widely used in LSI microprocessors and memories before CMOS processing matured. CMOS uses complementary pull-up and pull-down networks so that static power is ideally very low; current primarily flows during transitions, yielding excellent energy characteristics and battery suitability.

Step-by-Step Solution:

Verification / Alternative check:

Review of early microprocessors and memory chips shows NMOS implementations; later, CMOS displaced NMOS due to power and scaling advantages, especially in portable and high integration systems.

Why Other Options Are Wrong:

'NMOS, PMOS' mismatches the low power part. 'PMOS, CMOS' does not reflect LSI dominance. 'MOSFET, PMOS' mixes a device category with a subtype and misses low power preference.

Common Pitfalls:

Assuming current CMOS dominance implies it historically dominated early LSI or confusing speed with power across families without considering static current.

Final Answer:

NMOS, CMOS