ASIC cost comparison: How do design costs for standard-cell ASICs compare with those for MPGA (masked gate array) implementations when targeting the same functionality?

Introduction / Context:
Two common custom-silicon approaches are standard-cell ASICs and masked gate arrays (MPGAs). Both require masks and NRE (non-recurring engineering), but the level of customization and design effort differs, which affects overall cost and time to market.

Given Data / Assumptions:

• Standard-cell: custom synthesis, placement/routing of many distinct library cells, full custom mask set.
• MPGA: prefabricated transistor/gate base with customized interconnect masks.
• Comparable functionality is assumed for fair comparison.

Concept / Approach:
Standard-cell flows maximize optimization (area, power, speed) but require more intensive design, verification, and mask steps, raising NRE and schedule demands. MPGAs leverage a fixed base layer, customizing only metallization, which reduces design complexity and mask costs, albeit with less ultimate flexibility and density optimization.

Step-by-Step Solution:

Verification / Alternative check:
Industry cost models and vendor quotes consistently show standard-cell NRE exceeding gate array NRE for comparable complexity.

Why Other Options Are Wrong:

Common Pitfalls:
Ignoring volume economics; at very high volumes, per-unit cost may favor standard-cell despite higher NRE, but the question focuses on design cost, not unit cost.

Final Answer:
higher than