PLD array notation refresher In a typical programmable logic device (PLD) circuit (PROM, PAL, GAL), the interconnections to the fixed OR plane are shown using a simple graphical convention. In such PLD array diagrams, the inputs (product terms) feeding each OR gate are designated by which symbol or mark?

Introduction / Context:
Programmable logic device (PLD) arrays are drawn with repeated logic structures so designers can see how product terms are formed and then summed to implement Boolean functions. Understanding the diagram conventions used for the AND and OR planes helps you quickly read PAL/GAL/PROM block diagrams and debug or plan logic fits.

Given Data / Assumptions:

• The question refers to common PLD array drawings showing the AND plane feeding an OR plane.
• Each OR gate takes multiple product terms (the outputs of the AND plane).
• Standard drafting conventions mark programmable connections and OR inputs with concise symbols.

Concept / Approach:
In PLD artwork, a small filled circle (a dot) at a junction typically indicates an intentional electrical connection. In array-style PLD figures, dots explicitly mark where a product-term line ties into an OR-sum line or where a fuse/device element is present. The same approach is used in the AND plane to indicate programmed connections at intersections.

Step-by-Step Solution:

Verification / Alternative check:
Open any textbook depiction of a PAL or GAL macrocell. You will see the product-term lines and, where connected to an OR-gate input, a dot or fuse symbol is used to indicate an active connection.

Why Other Options Are Wrong:
A “bus” denotes multiple grouped signals but does not by itself indicate an individual OR input connection. A “single line” shows a wire but does not explicitly indicate a connection choice to the OR input. “4 inputs” is not a symbol; it is a quantity and does not answer the symbol/mark question.

Common Pitfalls:
Confusing bus notations or generic wire junctions with the explicit “dot” used to show a programmed connection into the OR gate. Another pitfall is assuming every line entering the OR block is connected; only dotted junctions indicate a selected connection.

Final Answer:
a dot