Flip-flop behavior near the active clock edge What is the condition called when flip-flop inputs change at the same instant the active clock edge occurs, risking an indeterminate or unintended output?

Introduction / Context:
Flip-flops sample inputs at an active clock edge. If inputs change too close to that edge, setup or hold time requirements can be violated, leading to uncertain behavior. Many curricula refer to the resulting hazard as a race or race condition, closely tied to metastability in practical devices.

Given Data / Assumptions:

• Inputs are changing as the clock edge arrives.
• Device requires finite setup and hold time margins.
• Violation of these margins triggers unpredictable or oscillatory outcomes.

Concept / Approach:
If data transitions occur within the aperture around the sampling edge, the storage nodes can enter a metastable state or produce unexpected toggling. This conflict between changing data and the latching action is commonly described as a race condition in many introductory texts on sequential logic.

Step-by-Step Solution:

Verification / Alternative check:
Manufacturers specify setup and hold in datasheets. Timing analysis ensures input edges avoid the sampling aperture; otherwise, failures consistent with racing or metastability appear in hardware tests.

Why Other Options Are Wrong:

• Toggling: normal behavior of a T or JK flip-flop, not a timing hazard description.
• Slave loading: not the standard name for this hazard.
• Pulse timing: generic phrase, not the accepted term for the race issue.

Common Pitfalls:
Using asynchronous input signals without synchronization, or ignoring clock-to-output, setup, and hold in timing closure.

Final Answer:
racing