SISO delay design – choosing clock for a required delay An 8-bit serial in/serial out shift register must provide a 20 µs total delay from input to serial output. What clock frequency is required?

Introduction / Context:
Shift registers are often used as delay elements. The total delay equals the number of stages times the clock period. Selecting the correct clock frequency is a common timing-design task.

Given Data / Assumptions:

• 8-bit SISO shift register.
• Required overall delay = 20 µs.
• Each clock advances data by one stage.

Concept / Approach:
Total delay = N * T, where N is the number of stages and T is the clock period. Frequency f = 1 / T. Solve for f using N = 8 and total delay given.

Step-by-Step Solution:

Verification / Alternative check:
Sanity check: An 8-stage pipeline at 400 kHz has period 2.5 µs; 8 periods is 20 µs, exactly as required.

Why Other Options Are Wrong:

• 40 kHz: Ten times too low; would yield 200 µs delay.
• 50 kHz: Too low; delay would be 160 µs.
• 500 kHz: Too high; delay would be 16 µs.

Common Pitfalls:

• Confusing 'bits' with 'bytes' or forgetting that each stage adds one full clock period.
• Unit conversion errors between µs and kHz.

Final Answer:
400 kHz