Parallel-to-serial transmission – must parallel data be converted into serial format before sending over a serial link?

Difficulty: Easy

Correct Answer: Correct

Explanation:


Introduction / Context:
Many systems collect data in parallel (multiple bits at once) but transmit over a single-wire or differential serial channel (UART, SPI single line, SERDES lanes). This raises a practical requirement: can parallel words traverse a serial medium directly, or must they be serialized first?


Given Data / Assumptions:

  • Source presents N-bit words simultaneously.
  • Channel offers one bit path per unit interval (serial).
  • We assume conventional digital transmission without exotic multi-wire bundling.


Concept / Approach:
A serial channel carries one bit per symbol time (per lane). Therefore, an N-bit parallel word must be converted to a time-ordered sequence of bits. The hardware block that does this is a parallel-in serial-out (PISO) shift register or a serializer. At the receiver, a serial-in parallel-out (SIPO) stage reconstructs the word boundaries. This conversion is independent of parity, speed grade, or cable impedance; those affect signal integrity and framing, not the necessity of serialization.


Step-by-Step Solution:

1) Latch an N-bit parallel word.2) Shift bits out in a defined order (MSB-first or LSB-first) via a PISO.3) Send over the serial medium with appropriate clocking/encoding.4) At the receiver, SIPO collects bits per clock and presents them in parallel again.


Verification / Alternative check:
UARTs, SPI, I2C, and high-speed SERDES all embody the same principle: data is serialized before line transmission and deserialized after reception, even if higher-level framing differs.


Why Other Options Are Wrong:
Parity mode, data rate, or cable impedance does not remove the need to serialize; they address error detection and physical layer aspects. Saying “Incorrect” would deny the definition of a serial channel.


Common Pitfalls:
Confusing multiple serial lanes aggregated in parallel (e.g., x4 links) with true parallel buses; each lane is still serial and requires serialization at some stage.


Final Answer:
Correct

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