S–R (Set–Reset) flip-flop disadvantage Which of the following is a key disadvantage of the basic S–R flip-flop (latch) implementation?

Introduction / Context:
The basic S–R flip-flop (or latch) is the simplest bistable memory element formed by cross-coupling two gates. While educational and useful, it suffers from a well-known drawback: a forbidden input combination that produces an indeterminate state. Understanding this limitation is crucial before moving to improved devices such as the J-K or D flip-flops.

Given Data / Assumptions:

• S–R latch realized with NOR gates (forbidden S = R = 1) or NAND gates (forbidden S = R = 0).
• Cross-coupled feedback holds state when inputs are inactive.
• No clocking; we are referring to the basic level-sensitive latch behavior.

Concept / Approach:

With cross-coupled logic, asserting both inputs simultaneously forces both internal nodes toward the same logic level, violating the requirement that Q and Q̄ be complements. After releasing the inputs, the final state can be unpredictable due to imbalances and propagation delays. This is often described as a forbidden or race condition, and is the main disadvantage of the simple S–R latch.

Step-by-Step Explanation:

Verification / Alternative check:

Truth tables of S–R latches always include a row flagged as “forbidden” or “invalid.” Simulation tools reproduce the metastability risk if both inputs are asserted together.

Why Other Options Are Wrong:

• No Enable input (a) and no clock input (c) are design choices; gated/clocked S–R variants exist.
• Single output (d) is incorrect; S–R latches provide complementary outputs Q and Q̄.
• Cannot be built from universal gates (e) is false; NAND/NOR gates are universal and commonly used.

Common Pitfalls:

• Confusing the S–R forbidden condition with the J–K flip-flop’s race-around problem.
• Assuming hardware will consistently resolve to the same state after a forbidden input; it may vary with temperature and timing.

Final Answer:

It has a RACE/forbidden condition when both inputs are asserted.