Reading PLD array diagrams — meaning of a “dot” at an array intersection On classic PLD schematic/array diagrams (AND-OR planes), what does a filled dot at the intersection of a line and a product/sum term signify?

Introduction / Context:
PLD documentation often shows a grid: input signals (and sometimes their complements) run one way; product terms run the other. Small dots indicate whether a connection exists between a signal line and a product/sum term. Understanding this notation is essential when interpreting fuse maps or logic array diagrams.

Given Data / Assumptions:

• The diagram is a PLD logic array (e.g., programmable AND plane).
• Dots indicate configuration at crosspoints.
• Programming sets or clears these connections.

Concept / Approach:
A “dot” marks a programmed connection at a crosspoint, meaning that the corresponding signal participates in the product term (or sum term, in a PLA). Erasing the dot means the connection is absent. In older fuse-link devices, blowing a fuse removes the connection; in EEPROM/Flash-based PLDs, a memory bit enables or disables it.

Step-by-Step Solution:

Verification / Alternative check:
Device manuals show sample arrays where adding/removing a dot changes the implemented Boolean expression.

Why Other Options Are Wrong:

• Non-changeable: contradicts programmability.
• Intersection of logic blocks: the grid is within a block, not between blocks.
• I/O point: unrelated to crosspoint programming.

Common Pitfalls:
Confusing polarity bubbles with programmable dots; bubbles indicate inversion, dots indicate connections.

Final Answer:
A point that is programmable