FLEX10K architecture — outputs available from a Logic Element (LE) In Altera’s FLEX10K devices, a Logic Element (LE) can drive which two on-chip interconnect resources directly?

Introduction / Context:
FLEX10K is a classic FPGA family in which each Logic Element (LE) resides inside a Logic Array Block (LAB). Understanding where LE outputs can be routed clarifies how local vs. global connectivity works in the device and why certain placements yield better timing.

Given Data / Assumptions:

• An LE is the basic logic + register resource inside a LAB.
• FLEX10K devices provide both local interconnect (within the LAB) and long/fast interconnect across LABs (often called FastTrack interconnect).
• The question asks for the two routing destinations an LE output may drive.

Concept / Approach:
LE outputs can be fed to neighboring LEs in the same LAB through the local LAB interconnect for short, low-delay routes, or they can be driven onto the device-wide FastTrack interconnect to reach distant LABs and I/O blocks. This dual routing strategy supports both dense local logic and broader chip-level connectivity.

Step-by-Step Solution:

Verification / Alternative check:
FLEX10K handbooks depict LE outputs feeding LAB local interconnect and the FastTrack network.

Why Other Options Are Wrong:

• “ON/OFF,” “Hi-Z/ON,” “Hi-Z/OFF” describe pin states, not routing resources.

Common Pitfalls:
Confusing I/O pin tri-state behavior with internal routing options.

Final Answer:
The LAB and the fast track