FPGA LUT basics — typical inputs and truth-table size In many mainstream FPGAs, a single look-up table (LUT) historically accepts how many inputs, and therefore stores how many truth-table entries (possible input combinations)?

Introduction / Context:
A look-up table (LUT) is the core combinational element in most FPGAs. It implements any Boolean function of k inputs by storing a truth table with 2^k entries and using the input vector as an address. Many classic FPGA families used 4-input LUTs, while newer devices often use 6-input or larger LUTs.

Given Data / Assumptions:

• We refer to common, historical mainstream devices (e.g., early Xilinx/Altera families).
• Each LUT output is one bit; the LUT stores 2^k configuration bits.
• The question asks for typical k and corresponding number of entries.

Concept / Approach:
If a LUT has k inputs, it must hold 2^k bits to represent all input combinations. For k = 4, this is 2^4 = 16 entries. Thus a single 4-input LUT stores 16 configuration bits that define its output for every possible 4-bit input pattern.

Step-by-Step Solution:

Verification / Alternative check:
Older Spartan/Cyclone families feature 4-input LUTs (16-bit truth tables); modern 6-input LUTs store 64 entries, but the question targets the “most” common historical baseline.

Why Other Options Are Wrong:

• 8,16: A LUT with 8 inputs would require 256 entries, not 16.
• 4,12 and 6,12: 12 is not a power of two; a proper LUT table size must be 2^k.

Common Pitfalls:
Assuming “outputs” means output pins; here it refers to truth-table entries stored in the LUT memory.

Final Answer:
4,16