Considering the basic S–R (Set–Reset) latch truth table, how many distinct VALID input combinations exist?

Introduction / Context:
The S–R (Set–Reset) latch is one of the simplest memory elements in digital logic. Its truth table illustrates which input combinations produce defined outputs and which are forbidden or invalid due to ambiguity or metastability risks.

Given Data / Assumptions:

• Inputs: S (set) and R (reset) with active-high behavior.
• Outputs: Q and Q̄ with the constraint Q = not(Q̄).
• We consider the simple, unclocked, active-high S–R latch.

Concept / Approach:
There are four theoretical input combinations: 00, 01, 10, and 11. Of these, three lead to valid, deterministic behaviors: 00 (hold previous state), 01 (reset), and 10 (set). The input 11 is invalid because it drives both set and reset simultaneously, forcing Q and Q̄ both low in NOR-latch form, violating complementarity upon release and risking metastability.

Step-by-Step Solution:
List inputs: S R = 00, 01, 10, 11.Map results: 00 → Hold; 01 → Reset; 10 → Set; 11 → Invalid.Count valid entries: 3.

Verification / Alternative check:
Standard textbooks and digital logic curricula define the 11 state as forbidden for NOR-based S–R latches (and 00 forbidden for NAND-based active-low versions). The count of valid states remains three for either implementation after mapping active levels correctly.

Why Other Options Are Wrong:

• 1 or 2 valid entries: Underestimates; both set and reset (plus hold) are valid.
• 4 valid entries: Overestimates; one combination is forbidden.

Common Pitfalls:

• Confusing active-high NOR latch with active-low NAND latch; the invalid combination flips, but count of valid entries stays three.
• Ignoring timing hazards when exiting the invalid state can cause indeterminate outputs.

Final Answer:
3