Digital timing parameter: The interval required for a logic gate's output to settle to a new logic level after an input change is called what?

Introduction / Context:
Timing parameters are crucial in synchronous and asynchronous digital system design. They determine how fast signals may change and still be correctly captured and interpreted by downstream circuitry.

Given Data / Assumptions:

• A logic gate responds to an input transition.
• We observe the time for the output to reflect the new logic state.
• Standard 50% thresholds are used to measure timing edges.

Concept / Approach:
Propagation delay (tpd) is the time between a defined input transition (usually 50% point) and the corresponding output transition reaching its 50% point. Specifications often include tPLH (LOW to HIGH) and tPHL (HIGH to LOW). Rise time and fall time describe edge slew at the output itself; setup time pertains to data arrival before a clock. Noise immunity is a measure of tolerance to noise, not a time.

Step-by-Step Solution:
Identify the event: input switches from one valid logic level to the other.Measure at 50% points on input and output waveforms.The elapsed time defines the propagation delay.Manufacturers provide typical and worst-case values for design margins.

Verification / Alternative check:
Use an oscilloscope with a common trigger on the input edge and measure Δt to the output 50% crossing; compare to datasheet tPLH/tPHL.

Why Other Options Are Wrong:
Rise time is output edge slew speed, not input-to-output delay.

Fanout is a loading metric (number of inputs driven).

Setup time applies to flip-flops, not combinational gates.

Noise immunity is not a timing parameter.

Common Pitfalls:
Confusing measurement thresholds; always use consistent 50% crossings for delay and 10–90% or 20–80% for rise/fall times as specified.

Final Answer:
propagation delay