memory-and-storage digital-electronics question and answers -Page 4

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Home Aptitude

1. Refer to the given figures (a) and (b). A logic analyzer is used to check the circuit in figure (a) and displays the waveforms shown in figure (b). The actual analyzer display shows all four data outputs, Q0-Q3. The analyzer's cursor is placed at position X and all four of the data output lines show a LOW level output. What is wrong, if anything, with the circuit?
Options
A. Nothing is wrong, according to the display. The outputs are in the open state and should show zero output voltage.
B. The circuit is in the READ mode and the outputs, Q0-Q3, should reflect the contents of the memory at that address. The chip is defective; replace the chip.
C. The circuit is in the mode and should be writing the contents of the selected address to Q0?Q3.
D. The Q0?Q3 lines can be either LOW or HIGH, since the chip is in the tristate mode in which case their level is unpredictable.

4. The reason the data outputs of most ROM ICs are tristate outputs is to:
Options
A. allow for three separate data input lines.
B. allow the bidirectional flow of data between the bus lines and the ROM registers.
C. permit the connection of many ROM chips to a common data bus.
D. isolate the registers from the data bus during read operations.

8. What is the major difference between SRAM and DRAM?
Options
A. DRAMs must be periodically refreshed.
B. SRAMs can hold data via a static charge, even with power off.
C. The only difference is the terminal from which the data is removed?from the FET Drain or Source.
D. Dynamic RAMs are always active; static RAMs must reset between data read/write cycles.

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