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Logic Gates problems

5. The gates in this figure are implemented using TTL logic. If the output of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.
Options
A. a steady LOW
B. a steady HIGH
C. an undefined level
D. pulses

6. The gates in this figure are implemented using TTL logic. If the output of the inverter has an internal open circuit, what voltage would you expect to measure at the inverter's output?
Options
A. Less than 0.4 V
B. 1.6 V
C. Greater than 2.4 V
D. All of the above

7. When does the output of a NOR gate = 0?
Options
A. Whenever a 0 is present at an input
B. Only when all inputs = 0
C. Whenever a 1 is present at an input
D. Only when all inputs = 1

8. The gates in this figure are implemented using TTL logic. If the input of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.
Options
A. a steady LOW
B. a steady HIGH
C. an undefined level
D. pulses

9. When does the output of a NAND gate = 1?
Options
A. Whenever a 0 is present at an input
B. Only when all inputs = 0
C. Whenever a 1 is present at an input
D. Only when all inputs = 1

10. A major advantage of ECL logic over TTL and CMOS is ________.
Options
A. low power dissipation
B. high speed
C. both low power dissipation and high speed
D. neither low power dissipation nor high speed

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