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Digital System Projects Using HDL problems

  • 1. A very critical dimension in project management is the time your boss will give you to complete the HDL project.

  • Options
  • A. True
  • B. False
    • Discuss
  • 2. In the keypad HDL encoder, NANDing of the columns is used to activate the freeze bit.

  • Options
  • A. True
  • B. False
    • Discuss
  • 3. In the keypad HDL encoder, the ts bit array represents a tristate buffer.

  • Options
  • A. True
  • B. False
    • Discuss
  • 4. In the digital clock project, a MOD-60 BCD counter is made from a MOD-10 counter cascaded to a MOD-6 BCD counter.

  • Options
  • A. True
  • B. False
    • Discuss
  • 5. In the keypad HDL encoder, as long as all columns are high the ring counter is enabled and counting.

  • Options
  • A. True
  • B. False
    • Discuss
  • 6. In the digital clock project, the ENT input and RCO output can be used for synchronous counter cascading.

  • Options
  • A. True
  • B. False
    • Discuss
  • 7. In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the edge trigger clock moves the display to 12:00:00.

  • Options
  • A. True
  • B. False
    • Discuss
  • 8. In the keypad HDL encoder, after releasing a key the ring counter resumes its counting sequence.

  • Options
  • A. True
  • B. False
    • Discuss
  • 9. In the frequency counter, a pulse shaper block is needed to ensure that the unknown signal, whose frequency is to be measured, will be compatible with the clock input for the counter block.

  • Options
  • A. True
  • B. False
    • Discuss
  • 10. The frequency counter measures frequency by enabling a counter to count the number of pulses of the incoming waveform during a precisely specified period of time called the sampling time.

  • Options
  • A. True
  • B. False
    • Discuss

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