Pull-up resistor purpose: In digital logic, a pull-up keeps a normally floating (high-impedance) input at a defined logic level. Which levels correctly describe this behavior?

Introduction / Context:
Floating inputs can wander unpredictably due to leakage and noise. A pull-up resistor biases a high-impedance input to a known logic state when no active driver is present. Understanding this is foundational for reliable digital design.

Given Data / Assumptions:

• Input can be undriven (tri-stated, open-collector/drain, or disconnected).
• Pull-up connects the node to VCC through a resistor.
• Active devices may still pull the line LOW when needed.

Concept / Approach:
With a pull-up, the node tends to HIGH by default. When an open-collector/open-drain output sinks current, the same node transitions to LOW. The resistor sets a bias current and limits short-circuit power when pulled LOW.

Step-by-Step Solution:

Verification / Alternative check:
Measure the node with no driver: it reads near VCC and is stable. When a sink turns on, it reads near 0 V.

Why Other Options Are Wrong:

• LOW, float: Describes pull-down behavior, not pull-up.
• clock, float: A clock is a signal type, not a level.
• pulsed, float: Pulse describes timing, not default logic state.

Common Pitfalls:
Using too strong (low-ohm) pull-ups causing high power dissipation, or too weak (high-ohm) values causing slow edges and susceptibility to noise.

Final Answer:
HIGH, float