Introduction / Context:
Programmable logic families differ primarily in which internal arrays (AND or OR) are field-programmable. Understanding these differences is key when choosing devices for sum-of-products logic implementations and product-term budgeting.
Given Data / Assumptions:
- PROMs have a fixed AND (decoder) array and a programmable OR array.
- PALs (Programmable Array Logic) feature a programmable AND array and a fixed (hard-wired) OR array.
- FPLAs/PLAs typically have both AND and OR arrays programmable.
Concept / Approach:
The question asserts the classic textbook distinction: PAL → programmable AND, fixed OR. PROM → fixed AND (as a decoder), programmable OR fuses. Recognizing this mapping lets designers predict resource use and optimal device choice.
Step-by-Step Solution:
Recall PROM structure: fixed AND (decoder), programmable OR fuses.Recall PAL structure: programmable AND product terms, hard-wired OR structure.Compare with the statement → matches PAL definition → accurate.
Verification / Alternative check:
Cross-check with vendor datasheets or digital design textbooks; the PAL definition is consistent across sources.
Why Other Options Are Wrong:
Incorrect: Contradicts widely accepted PAL architecture.Partially correct; depends on speed grade: Speed grade does not change array programmability.Ambiguous; neither array is programmable: Opposite of reality for PALs.
Common Pitfalls:
Confusing PAL with PLA/FPLA, where both arrays may be programmable.Assuming “programmable” refers to RAM-based LUTs (that is FPGA terminology).
Final Answer:
Correct
Discussion & Comments