In computer architecture, what does the Memory Address Register (MAR) hold during a read or write cycle?

Introduction / Context:
Processor datapaths separate “what to access” from “what value to move.” The Memory Address Register (MAR) and Memory Data Register (MDR) play complementary roles. Knowing which holds addresses versus data is foundational to understanding fetch/execute cycles and bus timing.

Given Data / Assumptions:

• Von Neumann-style CPU with distinct internal registers for address and data.
• MAR participates in both instruction fetch and data access.
• MDR (also called MBR) is the data counterpart.

Concept / Approach:
During any memory transaction, the CPU places the target address into the MAR. The memory subsystem uses that address to read or write. The actual value to be transferred moves via the MDR/MBR, not the MAR. Therefore, the MAR does not contain the instruction bytes or the data payload—only the location identifier.

Step-by-Step Solution:

Verification / Alternative check:
Architecture textbooks and timing diagrams show MAR lines wired to the address bus and MDR lines to the data bus, confirming their distinct roles.

Why Other Options Are Wrong:

• A copy of data: That is MDR, not MAR.
• The current instruction: That is Instruction Register after fetch.
• Hardware circuits that execute instructions: Describes the ALU/CPU, not MAR.
• None of the above: Incorrect because MAR holds the address.

Common Pitfalls:
Confusing MAR with MDR and thinking MAR stores the data value rather than the address identifier.

Final Answer:
The address of the memory location to be accessed (read or write)