Loaded voltage divider behavior: When a load resistance is attached to the output node of a DC voltage divider, the source must supply additional current. Evaluate this statement about source current increasing under load.

Introduction / Context:Voltage dividers are ubiquitous. However, the ideal unloaded divider assumption breaks once a load is connected. Understanding how loading alters currents and voltages helps in designing dividers with acceptable regulation and selecting buffer stages when needed.

Given Data / Assumptions:

• Two-resistor divider producing an output node.
• A finite load R_L is connected from the output node to ground (or return).
• DC steady-state analysis; resistors are linear.

Concept / Approach:The source current equals the sum of currents through all paths tied to the source. Without load, current is I_unloaded = V_in / (R_top + R_bottom). With load, the bottom resistor and R_L form a parallel network, decreasing the effective lower-leg resistance and increasing total divider current. Therefore, the source must deliver more current when a load is attached.

Step-by-Step Solution:

Verification / Alternative check:Select sample values and calculate currents with and without load; the loaded case always shows higher source current for any finite R_L.

Why Other Options Are Wrong:

• Incorrect / depends on meter type / AC only: The rule follows from resistance reduction; instrument type and DC vs AC (for resistors) do not reverse it.
• True only if R_L is larger than the bottom resistor: Regardless of R_L magnitude, any finite R_L in parallel reduces the effective resistance and increases current.

Common Pitfalls:Ignoring load interaction when specifying divider resistors; forgetting that heavier loading also drops the output voltage below the ideal unloaded value.

Final Answer:Correct