Ripple/parallel addition design: to build an m-bit binary adder that accepts two m-bit operands and a carry-in, how many full-adder cells are required in the standard ripple-carry configuration?

Introduction / Context:
A full adder adds three one-bit values: A, B, and carry-in, producing a one-bit sum and a carry-out. By cascading full adders, we can construct an m-bit ripple-carry adder that computes the sum of two m-bit operands. The number of stages determines latency and hardware cost.

Given Data / Assumptions:

• We are designing a basic ripple-carry (parallel) adder.
• Two m-bit inputs and an optional carry-in.
• Each stage handles one bit position and propagates carry.

Concept / Approach:
Each bit position requires a full adder because there is both bit addition and a potential carry from the previous less significant position. Therefore, for m bits, we need exactly m full-adder cells in series. A half adder would suffice only for the least significant bit if we guaranteed no carry-in, but standard parallel adders allow a carry-in, so all stages are full adders.

Step-by-Step Solution:
Define stage function: FA adds Ai, Bi, and Ci-1.Cascade from LSB to MSB with carry propagation.Count stages: one FA per bit → total = m FAs.Select “m.”

Verification / Alternative check:
Block diagrams in digital design show m 1-bit full adders for an m-bit ripple adder; only specialized designs (carry-lookahead, carry-skip) alter carry logic, not the count of sum cells.

Why Other Options Are Wrong:
m/2: too few; would cover only half the bits.m-1: would omit one necessary stage.m+1: unnecessarily adds hardware.None: a correct choice exists.

Common Pitfalls:
Confusing half adders with full adders at the LSB; overlooking the carry-in requirement that standardizes all stages as full adders.

Final Answer:
m