Memory width expansion – composing an 8 k × 8 from 8 k × 1 devices How many separate 8 k × 1 RAM chips are required to build a memory with word capacity 8 k and word length 8 bits (i.e., 8 k × 8)?

Introduction / Context:
Designers often widen memory data paths by placing multiple narrow RAM ICs in parallel. This question tests the principle of data width expansion without changing address depth.

Given Data / Assumptions:

• Available IC: 8 k × 1 (8,192 addresses, 1 data bit each).
• Target memory: 8 k × 8 (8,192 addresses, 8 data bits each).
• All devices share the same address and control lines to maintain identical depth.

Concept / Approach:
To increase word length from 1 bit to 8 bits while keeping the same number of addresses, connect eight identical 8 k × 1 chips in parallel on A0..A12 and control pins. Each chip supplies one bit of the 8-bit data bus (D7..D0).

Step-by-Step Solution:

Verification / Alternative check:
A quick block diagram shows eight chips with common address and enable signals, outputs OR rather “wired” onto separate data lines forming an 8-bit bus.

Why Other Options Are Wrong:

• Four / Two / One: Would result in 4, 2, or 1 data bits per word, not the required 8.

Common Pitfalls:

• Confusing “depth increase” (cascading addresses) with “width increase” (parallel data lines).

Final Answer:
Eight