In digital memory and addressability theory, if a memory has N address lines, what is the correct general formula for memory capacity in addressable locations?

Introduction / Context:
Understanding how address lines translate into memory capacity is fundamental in computer architecture. Each address line is a binary signal that can represent two states. Together, N independent address lines can encode a certain number of unique addresses. This concept underlies RAM sizing, ROM mapping, and memory-mapped I/O design in embedded and general-purpose computing systems.

Given Data / Assumptions:

• N is the number of independent address bits.
• Each address uniquely selects one location (addressable unit).
• We are counting the number of distinct addresses, not the byte size per location.

Concept / Approach:

If there are N binary address lines, each can be 0 or 1. The Cartesian product of these possibilities yields the total number of unique address patterns. Because the choices multiply, the count of unique addresses equals 2 raised to the power of N. If each location stores, for example, one byte, then the total bytes equal (2^N) * 1 byte; for wider words, multiply by word size.

Step-by-Step Solution:

Verification / Alternative check:

Example: With N = 10 address lines, MC = 2^10 = 1024 addresses. With N = 20, MC = 2^20 ≈ 1,048,576 addresses. This matches conventional RAM sizing (K, M, G scales).

Why Other Options Are Wrong:

MC = N/2 or 2/N incorrectly implies linear or inverse relationships.

MC = N^2 is polynomial, not exponential, and fails real examples.

“None” is wrong because a standard formula exists.

Common Pitfalls:

Confusing address lines with data lines. Data bus width affects bytes per location, not the number of addresses. Also, mistaking 2^N addresses for 2^N bytes without considering word size leads to errors.

Final Answer:

MC = 2^N