Understanding the flash (parallel) ADC principle The flash method of analog-to-digital conversion uses an array of comparators that compare reference voltages with the analog input voltage to generate a thermometer code.

Introduction / Context:
Flash (parallel) ADCs are renowned for extremely high conversion speeds. They achieve this by using many comparators operating in parallel to compare the input against a ladder of reference voltages, producing a thermometer code that is then encoded into binary.

Given Data / Assumptions:

• An N-bit flash ADC employs 2^N - 1 comparators.
• A resistor ladder generates evenly spaced reference levels.
• Digital encoding logic converts the thermometer pattern to binary output.

Concept / Approach:
Each comparator outputs 1 if Vin exceeds its reference and 0 otherwise. The boundary where outputs switch indicates the quantization level. Because all comparisons happen simultaneously, latency is only the comparator and encoder delay, making flash the fastest ADC architecture.

Step-by-Step Solution:

Verification / Alternative check:
Sweep Vin from 0 to Vref and verify monotonic step transitions at expected thresholds; check DNL/INL using measured transition points.

Why Other Options Are Wrong:
“Incorrect” contradicts the flash architecture. The other options refer to unrelated converter types or bit depths.

Common Pitfalls:
High power and large area due to many comparators; input kickback; encoder bubble errors requiring bubble-correction logic.

Final Answer:
Correct