FPGA/PLD tool flow In a typical programmable logic device workflow (synthesis → fitting/place-and-route → bitstream generation → …), what is the final step that actually configures the target device?

Introduction / Context:
Designing for FPGAs or CPLDs involves multiple software steps before the design runs on silicon. Newcomers often confuse offline steps (simulation, synthesis, place-and-route) with the step that physically programs the device. Clarifying this order avoids costly lab time and misdiagnoses when a board appears unresponsive.

Given Data / Assumptions:

• The standard flow includes simulation, synthesis, implementation (fitting/place-and-route), and bitstream generation.
• Programming cables (JTAG/USB-Blaster/Platform Cable) or configuration memories are used for final configuration.
• Terminology varies by vendor (programming, configuring, downloading), but the concept is the same.

Concept / Approach:
Synthesis translates HDL to a technology-mapped netlist. Implementation places and routes that netlist into the device resources. Bitstream generation produces a configuration file (for example, .bit, .sof, .pof). None of those steps alone configures the chip. The design only becomes active after the configuration image is transferred to the device (or to a companion configuration flash) via a download/programming step.

Step-by-Step Solution:

Verification / Alternative check:
In vendor tools (for example, Quartus, Vivado), the final action that changes board behavior is the “Program/Configure Device” step, confirming that downloading is the last step that actually applies the design.

Why Other Options Are Wrong:

• compiling / synthesis: These are software steps that create a bitstream but do not load it onto the device.
• simulation: Verifies function but does not affect hardware configuration.

Common Pitfalls:
Assuming that a successful bitstream build automatically configures the device, or forgetting to select the correct cable/chain, which leaves the old design running.

Final Answer:
downloading