Question 1

EPROM erase granularity — is the key advantage of EPROM the ability to erase a single byte independently?

Accepted Answer

Introduction / Context: EPROM (Erasable Programmable Read-Only Memory) and EEPROM have similar-sounding names but very different erase mechanisms. EPROM devices are erased by ultraviolet (UV) light through a quartz window and the erase operation clears the entire chip at once. EEPROM and Flash enable electrical erase of bytes, words, or blocks. Given Data / Assumptions: The claim is that EPROM’s advantage is single-byte erase capability. We consider standard UV-erasable EPROMs and OTP-EPROMs. Erase granularity is the focus, not program granularity (programming is byte-oriented). Concept / Approach: EPROM stores charge on floating gates. UV photons discharge all cells simultaneously when exposed for the specified time, returning the device to the erased (all 1s) state. No byte-level selective erase exists in EPROM. EEPROM (Electrically Erasable PROM) allows in-circuit, selective electrical erase—often at the byte or page level—without UV exposure, which is its key advantage for small updates. Step-by-Step Solution: Identify device type: EPROM vs EEPROM.Recap EPROM erase: bulk UV exposure through window.Recap EEPROM erase: electrical byte/page/block erase.Conclude the statement about EPROM single-byte erase is incorrect. Verification / Alternative check: Look at EPROM datasheets (e.g., 27C256, 27C512): specify UV erase procedure and time; no byte erase command exists. EEPROM datasheets list byte/page erase/write commands. Why Other Options Are Wrong: “Correct via window”/“correct for electrically erasable EPROM”: confuses EPROM with EEPROM.“Only on OTP”/“depends on package”: OTP parts cannot be erased at all; package type does not change erase granularity. Common Pitfalls: Mixing programming granularity (byte writes) with erase granularity; conflating EPROM and EEPROM terminology. Final Answer: Incorrect — EPROM erases the whole device via UV exposure

Question 2

Memory map — a “memory map” is an address diagram that shows address ranges and boundaries across a system’s address space. Is this description accurate?

Accepted Answer

Introduction / Context: A memory map is foundational documentation for embedded systems, CPUs, and SoCs. It tells firmware developers which address regions correspond to RAM, ROM/Flash, peripherals, and reserved areas. Without a correct memory map, code cannot reliably access devices or storage, and linker configurations would be guesswork. Given Data / Assumptions: The statement frames a memory map as an address-listing diagram showing boundaries of the address space. We assume a flat, linear address space typical of many MCUs/MPUs. Peripherals may be memory-mapped into specific ranges. Concept / Approach: The memory map defines start and end addresses for each region and often annotates access width, privileges, and caching/buffering attributes. It may also indicate boot vectors, interrupt tables, and special-function registers. Maps are used by toolchains (linker scripts) and by board support packages to set up MMU/MPU attributes and to avoid conflicts between code, data, and I/O regions. Step-by-Step Solution: Interpret “map” literally: a visual/tabular representation of address regions.Identify boundaries: each block shows base address and size/end address.Relate to system design: use the map to place firmware sections (text/data/stack/heap).Conclude the description is accurate. Verification / Alternative check: Review any MCU reference manual: memory maps appear early, listing Flash, SRAM, and peripheral base addresses used by drivers and startup code. Why Other Options Are Wrong: Microcontroller-only or cache-only claims are too narrow; memory maps apply widely and concern addresses, not speeds.“Inaccurate”: contradicts standard documentation practice. Common Pitfalls: Confusing memory maps with address decoding schematics; ignoring endianness and bus width which are separate concerns. Final Answer: Accurate (Correct)

Question 3

Addressing — the unique number that specifies the location of data in memory is called its _____.

Accepted Answer

Introduction / Context: Every readable/writable location in a random-access memory is indexed by a unique identifier so the processor or controller can select it. This identifier enables decoders inside the memory to select a row/column and present the corresponding data to the bus interface. Given Data / Assumptions: The blank refers to “the unique representation of the location.” We assume a random-access model with discrete, addressable locations. The question is about naming, not encoding details. Concept / Approach: An address is the label for a memory location. On the hardware side, address lines carry the binary value of the selected location; internally, decoders translate this value to activate a word line and select bit lines. Software presents addresses as pointers, offsets, or virtual addresses that are mapped to physical ones via MMU/MPU logic when present. Step-by-Step Solution: Identify the needed term from context: unique locator → address.Relate to hardware: A0…An lines form a binary number selecting a location.Relate to software: pointers/indices reference addresses to access data.Conclude the blank is “address.” Verification / Alternative check: Any memory datasheet lists “address pins” and specifies address setup/hold timing tied to location selection, reinforcing the definition. Why Other Options Are Wrong: Opcode: encodes an instruction, not a location.Checksum/parity: error detection, not location ID.Mask: used for bitwise selection, not for location identification. Common Pitfalls: Confusing “data” with “address”; they travel on separate buses in many architectures (or time-multiplexed on a shared bus in some designs). Final Answer: Address

Question 4

Selecting a memory type for small, occasional read/write updates — which technology is typically used when only a small amount of non-volatile read/write storage is required?

Accepted Answer

Introduction / Context: Designers often need to store configuration parameters, calibration constants, or user settings that must persist without power yet be updateable occasionally in the field. The memory choice must balance non-volatility, endurance, write granularity, interface simplicity, and cost. Given Data / Assumptions: Requirement: small amount of read/write storage with non-volatile retention. Updates are occasional, not continuous high-throughput logging. Low pin count and in-circuit programmability are preferred. Concept / Approach: EEPROM (Electrically Erasable PROM) allows byte/page-level electrical erase and write in-circuit, with typical endurance ratings from tens of thousands to millions of cycles per location and data retention for years. PROM and Mask ROM are one-time or factory programmed (not rewriteable). SRAM and DRAM are volatile; they lose content without power and therefore do not meet the non-volatile requirement for persistent settings without a battery. Step-by-Step Solution: Identify non-volatile and rewriteable requirement → rules out SRAM/DRAM.Eliminate one-time technologies (PROM/Mask ROM).Recognize EEPROM’s byte-level erase/write advantage for small updates.Select EEPROM as the best fit for small, occasional R/W needs. Verification / Alternative check: Microcontroller reference designs commonly pair EEPROM for parameter storage or emulate EEPROM in Flash when no discrete EEPROM is used, underscoring its role for small, occasional updates. Why Other Options Are Wrong: PROM/Mask ROM: not electrically rewriteable in the field.SRAM/DRAM: volatile; require continuous power or refresh and lose data when power is removed. Common Pitfalls: Confusing EEPROM with EPROM; assuming Flash always suits tiny updates—Flash typically erases in blocks, making EEPROM more convenient for small records. Final Answer: EEPROMs

Question 5

DRAM maintenance — the periodic recharging of dynamic RAM storage cells is known as _____.

Accepted Answer

Introduction / Context: Dynamic RAM stores each bit as charge on a tiny capacitor. Because capacitors leak over time, stored charge decays, jeopardizing data integrity. To preserve data, systems must periodically restore the charge on each cell—this maintenance process is fundamental to DRAM operation and system memory controllers. Given Data / Assumptions: The blank asks for the term describing periodic cell recharging. We consider commodity DRAM and embedded DRAM alike. Timing windows (e.g., 64 ms) are typical, but the exact interval varies by device. Concept / Approach: “Refreshing” is the standardized term. The memory controller issues refresh commands that cycle through all rows, reading and immediately restoring each cell’s charge. Address multiplexing is a separate design choice to reduce pin count; bootstrapping relates to circuit techniques; “flashing” refers to Flash memory operations; “scrubbing” usually means background error checking/correction, not the fundamental DRAM charge restore process. Step-by-Step Solution: Identify stored-bit mechanism: capacitor charge decays → needs restoration.Name the periodic process: “refreshing.”Recognize controller involvement: auto-refresh/self-refresh modes exist.Confirm alternatives are unrelated to charge restoration. Verification / Alternative check: DRAM datasheets specify refresh rates and include commands like REFRESH or AUTO REFRESH; power-down self-refresh modes keep data with minimal power. Why Other Options Are Wrong: Multiplexing: technique to time-share row/column address pins.Bootstrapping: circuit trick to momentarily exceed supply or enhance gate drive.Flashing: operation for Flash/EPROM/EEPROM, not DRAM.Scrubbing: background ECC maintenance, not basic DRAM refresh. Common Pitfalls: Assuming “refresh” equals “read”; although reads restore charge on accessed rows, dedicated refresh cycles are still required to cover all rows within the retention window. Final Answer: Refreshing

Question 6

Row/column pin sharing in DRAM — the technique that reuses the same external pins to carry first the row address and then the column address is called _____.

Accepted Answer

Introduction / Context: To keep packages small and costs low, DRAM devices reduce the number of address pins by time-multiplexing the address bus. Instead of dedicating separate pins to all row and column bits, the same pins are driven twice—first with the row portion, then with the column portion—latched by distinct strobes. Given Data / Assumptions: The question asks for the name of this pin-sharing technique. We assume conventional DRAM signaling with RAS (Row Address Strobe) and CAS (Column Address Strobe). Focus is on external pin reuse, not internal banking or refresh. Concept / Approach: “Address multiplexing” is the correct term. During a DRAM access, the controller presents the row address and asserts RAS to latch it, then presents the column address and asserts CAS. This allows, for example, a device with 12 row + 10 column bits (22 total) to expose only 12 pins externally and reuse them, dramatically easing pin count and package size. Step-by-Step Solution: Identify need: reduce address pin count on DRAM packages.Describe method: present row on pins → latch with RAS; present column → latch with CAS.Name technique: address multiplexing.Differentiate from other concepts: refresh, strobes, and interleaving are related but not identical. Verification / Alternative check: Any DRAM timing diagram shows separate RAS and CAS phases with the same address pins carrying different portions, confirming the multiplexing behavior. Why Other Options Are Wrong: Flash conversion: unrelated to DRAM addressing.Dynamic refresh: maintenance process, not pin reuse scheme.Address strobe: a control signal (RAS/CAS), not the multiplexing method itself.Bank interleaving: access scheduling across banks, not pin multiplexing. Common Pitfalls: Confusing the control signals (RAS/CAS) with the overall technique; assuming multiplexing applies to data pins—here it specifically refers to address pins. Final Answer: Address multiplexing

Question 7

Semiconductor memory timing definition: What is the term for the time interval between a memory device receiving a valid new address on its inputs and the corresponding data becoming available at the data outputs (valid to read)?

Accepted Answer

Introduction / Context: When working with semiconductor memories (SRAM, DRAM, ROM, and their derivatives), timing parameters define how quickly a processor or controller can obtain valid data. One of the most fundamental parameters is the interval from presenting an address to the memory until the output data is valid and stable. This concept is crucial for bus timing, wait-state insertion, and overall system performance. Given Data / Assumptions: A new address is applied to a memory chip’s address pins. Appropriate control signals (chip enable, output enable) are asserted. We are interested in the time until data outputs provide correct, stable data. Concept / Approach: The standard timing term for address-to-data latency is access time. It specifies how long after a valid address (and enables) the memory guarantees valid data at its outputs. Designers compare access time with the processor’s cycle time to determine whether wait states are needed. Do not confuse this with bus speed (a system-level metric) or generic read/write “speed,” which are not formal timing parameters in datasheets. Step-by-Step Solution: Identify the event: new valid address appears at the memory.Identify the outcome: data becomes valid at DQ pins.Match to standard datasheet term: address-to-data specification is the memory’s access time.Therefore, the correct term for this interval is access time. Verification / Alternative check: Open any SRAM/DRAM/ROM datasheet: the principal read timing is listed as tACC or similar, defined from address (and control) valid to data valid. This aligns exactly with the scenario in the stem. Why Other Options Are Wrong: Bus speed: a system-wide interface rate, not a device timing. Read/write speed: informal and ambiguous. Write/data speed: not a standard timing term. Address setup time: the minimum time address must be stable before a strobe, not the address-to-data latency. Common Pitfalls: Confusing tACC with tOE (output enable to data valid) or with synchronous timing (clock-to-Q in SDRAM/DDR). Always read the specific timing diagrams. Final Answer: Access time

Question 8

Read/write memory identification: Which of the following is a standard example of read/write (random-access, user-alterable during normal operation) semiconductor memory?

Accepted Answer

Introduction / Context: Semiconductor memories are commonly grouped into read/write memories and read-mostly or read-only memories. Read/write memory typically refers to RAM used as working storage in computers and embedded systems. Recognizing which technologies are volatile, nonvolatile, erasable, or one-time programmable is basic to memory selection and system design. Given Data / Assumptions: Read/write memory here means memory freely writable and readable during normal system operation. Standard device categories: RAM, PROM, EEPROM, Mask ROM (MROM), Flash. General textbook conventions are assumed. Concept / Approach: RAM (Random-Access Memory) is the canonical read/write memory: the processor can store and retrieve data at any time during normal operation. PROM and MROM are programmed once (PROM by the user with a programmer; MROM at the factory). EEPROM and Flash are nonvolatile and electrically erasable, but not typically written as frequently as RAM during normal program execution; their writes are slower and follow erase-program cycles. Step-by-Step Solution: Define the class: read/write ≈ operationally alterable, random access, frequent updates.Classify options: RAM fits; PROM/MROM are not repeatedly writable; EEPROM/Flash are rewritable but not used as the primary read/write working store.Select RAM as the best, standard example. Verification / Alternative check: Typical architectures: program/data execute in RAM; firmware or configuration data reside in nonvolatile memories (Flash/EEPROM) updated infrequently. This separation confirms RAM as the intended answer. Why Other Options Are Wrong: PROM and MROM are not rewritable in-system. EEPROM and Flash are rewritable but slow, endurance-limited, and usually not used for general-purpose working memory. Common Pitfalls: Equating “electrically erasable” with the same role as RAM; although writable, EEPROM/Flash have different performance and usage models. Final Answer: RAM

Question 9

ROM terminology: What is the common term for the process of entering or installing data/patterns into a ROM device (especially a PROM), as performed with a programmer?

Accepted Answer

Introduction / Context: Read-Only Memories (ROMs) come in several forms: mask-programmed at the factory, one-time programmable PROMs, and erasable devices. The act of placing data into a PROM or EPROM with an external programmer is commonly referred to in industry shorthand as “burning” a ROM image, even though modern devices are not literally burned. Understanding the lingo helps when reading legacy documentation and tool instructions. Given Data / Assumptions: We refer to user programming of PROM/EPROM/EEPROM with a device programmer. Colloquial yet widely used terminology is acceptable. Mask ROM (MROM) is programmed during fabrication and is not field-programmable. Concept / Approach: Entering data into a user-programmable ROM has long been called “burning” a ROM. While “programming” is the formal term, technician and manufacturing vernacular often uses “burn,” “ROM burn,” or “burn-in.” Note that strict reliability engineering uses “burn-in” to mean stress testing components; however, many exam contexts accept “burning” or “burning in” to mean programming a PROM. Among the provided choices, “burning in” best matches the intended meaning. Step-by-Step Solution: Identify the action: write a fixed image into a ROM device using a programmer.Match common terms: “programming a ROM” a.k.a. “burning a ROM.”From the available options, select “Burning in.” Verification / Alternative check: Legacy EPROM/EEPROM programmer manuals describe the operation as programming/burning a device with a HEX image. Mask ROMs, by contrast, are defined at fabrication via masks, not burned by the user. Why Other Options Are Wrong: Configuration and addressing are operational behaviors, not the one-time image write step. Internal decoding is a ROM’s architectural feature. Masking at fabrication applies to MROM, not field programming. Common Pitfalls: Confusing “burn-in” (reliability stress) with “burning” a ROM. Despite the overlap, exam contexts frequently use “burning” to mean programming PROM/EPROM. Final Answer: Burning in

Question 10

DRAM refresh interval (typical legacy specification): Refreshing a dynamic RAM (DRAM) cell array typically must occur about every ____ to prevent charge loss from the storage capacitors.

Accepted Answer

Introduction / Context: Unlike SRAM, DRAM stores each bit as charge on a tiny capacitor, which leaks over time and must be periodically refreshed. The refresh interval is a key parameter: controllers must cycle through all rows before the charge decays below a reliable threshold. While modern DRAM families specify different intervals (for example, on the order of tens of milliseconds), many foundational texts and legacy exam questions cite a much shorter, illustrative interval for simplicity. Given Data / Assumptions: Classic/legacy DRAM context used in many electronics quizzes. We seek a typical refresher interval value from those provided. Goal is to prevent data loss due to charge leakage. Concept / Approach: DRAM cells lose charge exponentially. A refresh controller (internal or external) ensures each row is refreshed within the specified maximum interval. Many academic sources historically use ≈2 ms as a teaching value for “must refresh periodically,” even though specific commercial parts may list values such as 4 ms, 8 ms, or 64 ms total across all rows. From the given choices, 2 ms fits the classic requirement often quoted in fundamentals questions. Step-by-Step Solution: Recognize that DRAM requires periodic refresh to maintain data integrity.Select the most commonly taught legacy figure among the options.From the choices provided, 2 ms matches the classic teaching value.Therefore, choose 2 ms as the answer in this context. Verification / Alternative check: Examine traditional exam prep materials: many specify 2 ms, while modern JEDEC parts may state 64 ms (or temperature-dependent values). The question’s option set and phrasing indicate the simpler legacy figure is expected. Why Other Options Are Wrong: 2 µs and 8 µs are far too short for typical DRAM; 8 ms or larger can be correct for some devices but are not the historical “textbook” value used in basic quizzes like this one. Common Pitfalls: Assuming a single universal number; in practice, always consult the specific DRAM’s datasheet and temperature derating tables. Final Answer: 2 ms

Question 11

Pin-count reduction technique in memory ICs: To keep the package pin count manageable while addressing large arrays, manufacturers commonly use which technique on address lines?

Accepted Answer

Introduction / Context: Large memory arrays require many address lines. To avoid packages with impractically high pin counts, memory manufacturers employ techniques to present addresses in phases, drastically reducing the number of physical pins while still reaching every cell. Understanding this method is essential for interfacing DRAM and SDRAM parts that separate row and column addressing. Given Data / Assumptions: Goal: fewer package pins while still accessing a large address space. Typical memories: DRAM families separate row and column addressing. Controllers provide strobes that qualify each phase of the address. Concept / Approach: Address multiplexing sends part of the address (row) during one phase and the remaining part (column) during another, using the same physical pins. Row Address Strobe (RAS) and Column Address Strobe (CAS) latch each portion internally. This halves the number of address pins compared with providing the entire address in parallel, enabling compact packages and lower costs. Step-by-Step Solution: Identify the constraint: package pin count vs. address width.Apply the technique: multiplex the address over time on the same pins.Recognize standard control signals: RAS latches row; CAS latches column.Therefore, the correct term is address multiplexing. Verification / Alternative check: DRAM datasheets show A0–An pins used for both row and column, with RAS/CAS strobes. SRAMs without multiplexing typically require more pins or smaller densities. Why Other Options Are Wrong: MOSFET architecture is generic device physics. Address decoding is internal selection logic, not a pin-saving method. Demultiplexing is the inverse operation at the receiver. On-chip PLLs relate to clocks, not address pin reduction. Common Pitfalls: Confusing address multiplexing with time-multiplexed data; note that some buses multiplex address and data as well, but the question is specifically about address lines within memory ICs. Final Answer: Address multiplexing

Question 12

EEPROM data characteristics: The binary information stored in an EEPROM device is best described as which of the following?

Accepted Answer

Introduction / Context: Electrically Erasable Programmable Read-Only Memory (EEPROM) is a nonvolatile memory technology used for configuration, calibration constants, and small data logs. Understanding whether the data is volatile, permanent, or erasable helps in selecting storage for embedded systems and firmware updates. Given Data / Assumptions: EEPROM retains data without power (nonvolatile). It can be reprogrammed electrically in-system. Erase/write operations are slower and wear-limited compared to RAM writes. Concept / Approach: The defining feature of EEPROM is that stored information persists with power removed and can be erased and rewritten electrically. Therefore, among the options given, “erasable” captures the essential capability. Calling it “permanent” would be misleading because the device’s very purpose is reprogrammability. It is not volatile, and it does not require periodic refresh like DRAM. Step-by-Step Solution: Classify the memory: nonvolatile and reprogrammable.Map characteristics to choices: “erasable” is the operative property.Conclude the correct description is “Erasable.” Verification / Alternative check: EEPROM datasheets describe erase/write cycles, endurance (e.g., 100k+ cycles), and data retention (e.g., 10 years), reinforcing that data is both nonvolatile and erasable. Why Other Options Are Wrong: Volatile: incorrect; EEPROM holds data without power. Permanent: incorrect; data can be erased. Refreshed: not required (that is DRAM behavior). Dynamic only during power-on: not a standard description. Common Pitfalls: Confusing EEPROM with ROM (truly fixed) or with Flash (block-erase, similar concept but different erase granularity and speeds). Final Answer: Erasable

Question 13

Mask ROM (MROM) data attribute: In a mask-programmed ROM, the stored data pattern is considered to be which of the following over the lifetime of the device?

Accepted Answer

Introduction / Context: Mask ROM (MROM) devices are programmed during semiconductor fabrication using photolithographic masks. They are cost-effective at very high volumes but cannot be altered after manufacture. Selecting the correct memory type depends on whether the content must be field-updatable or fixed forever. Given Data / Assumptions: MROM content is defined during wafer processing. No electrical erase or reprogram capabilities exist. Use cases include fixed firmware for mass-produced devices. Concept / Approach: Because the bit pattern is physically encoded in the silicon by masks, the data is effectively permanent for the life of the device. There is no refresh requirement, and data does not disappear when power is removed (nonvolatile). Any change requires a new mask set and fabrication run, not a field operation. Step-by-Step Solution: Identify programming method: photomasks during manufacture.Recognize consequence: no field erase or write.Therefore, the data is best described as permanent. Verification / Alternative check: Compare to PROM/EPROM/EEPROM/Flash: all are field-programmable to varying degrees; MROM is not. Datasheets and textbooks consistently call MROM content permanent. Why Other Options Are Wrong: Volatile: incorrect; MROM is nonvolatile. Erasable/Temporary/Battery-backed only: do not describe mask-defined, unchangeable content. Common Pitfalls: Assuming “ROM” always means erasable (e.g., EEPROM); only certain ROM types support electrical erasure. Final Answer: Permanent

Semiconductor Memory Questions