Question 1

Functional blocks — a typical monolithic operational amplifier includes (at minimum) an input differential amplifier, a high-gain intermediate/voltage amplification stage, and an output buffer/driver. Is this characterization appropriate?

Accepted Answer

Introduction / Context:Despite wide variation among families, most general-purpose op-amps share a recognizable internal architecture: a differential input stage for high input impedance and common-mode rejection, one or more high-gain intermediate stages, and an output stage capable of driving loads. Recognizing these blocks helps explain datasheet parameters such as input offset, open-loop gain, slew rate, and output swing. Given Data / Assumptions: Monolithic op-amp intended for linear amplification from DC into the kHz–MHz range, subject to device limits. Closed-loop operation with negative feedback is typical in application. Additional blocks (bias networks, protection, compensation) may be present but do not change the core three-stage view. Concept / Approach:The input differential pair compares the two input voltages and converts their difference into a current/voltage signal while rejecting common-mode components. A high-gain stage (often a Miller-compensated voltage amplifier) provides most of the open-loop gain and sets the dominant pole for stability. The output stage buffers the high-gain node, supplies current, and reduces output impedance, enabling the op-amp to drive external loads and feedback networks robustly. Step-by-Step Solution: 1) Identify the differential input pair and associated current mirrors (sets input behavior and CMRR).2) Note the high-gain intermediate amplifier with compensation capacitor (sets A_OL and bandwidth).3) Recognize the output emitter follower or push-pull stage (sets drive and swing limits).4) Map datasheet specs (A_OL, SR, Rout) back to these stages for intuition. Verification / Alternative check:Block diagrams in op-amp datasheets routinely depict this three-stage arrangement; application notes explain how each stage contributes to closed-loop behavior and stability. Why Other Options Are Wrong: “Incorrect” contradicts common architectures.Limiting to discrete or rail-to-rail devices ignores that this structure spans many technologies.Package type does not determine internal stage topology. Common Pitfalls:Assuming the presence of AC coupling between stages; forgetting that compensation and protection circuitry are support functions, not replacements for the core stages. Final Answer:Correct

Question 2

Closed-loop gain dependence — in a linear op-amp circuit, does changing the input voltage alter the circuit’s closed-loop voltage gain, or is the gain set by the feedback network (until nonlinearity or saturation occurs)?

Accepted Answer

Introduction / Context:For op-amps operated with negative feedback in their linear region, the closed-loop voltage gain is determined by the feedback network, not by the instantaneous input level. This distinction prevents a common misconception that “turning up the input” changes gain; it changes output amplitude until a limit is reached, but the ratio Vout/Vin remains set by the feedback. Given Data / Assumptions: Standard inverting or non-inverting closed-loop configuration. Operation within linear limits (no output saturation or slew-rate limiting). Bandwidth and phase margin are adequate for the intended frequency range. Concept / Approach:In a non-inverting amplifier, Av = 1 + (Rf/Rg). In an inverting amplifier, Av = −Rf/Rin. These gains do not depend on Vin; they are functions of resistor ratios. If Vin increases, Vout increases proportionally as long as the op-amp can supply the required voltage and current. When limits are exceeded (clipping, current limit, slew rate), the effective “gain” appears to change only because the amplifier is no longer linear. Step-by-Step Solution: 1) Identify the feedback network that sets the closed-loop transfer function.2) Write the gain expression in terms of component values.3) Vary Vin conceptually; Vout scales according to the fixed gain until limits are reached.4) Recognize non-idealities (finite A_OL, bandwidth) introduce small gain error but do not make gain depend on Vin directly. Verification / Alternative check:Measure Vout/Vin for several input amplitudes within the linear region; the ratio remains essentially constant. Distortion and clipping occur only near output or input headroom limits. Why Other Options Are Wrong: Claims that input level changes gain confuse amplitude with the fixed transfer ratio.Device type, frequency extremes, or package style do not by themselves make gain a function of Vin. Common Pitfalls:Attributing clipped or slewed waveforms to “gain change”; forgetting that saturation and slew limits are nonlinear behaviors outside closed-loop linear assumptions. Final Answer:Incorrect — closed-loop gain is set by the feedback network, not by input amplitude (within linear range).

Question 3

Operational amplifiers — understanding the “virtual ground” node: In an ideal inverting amplifier configuration, the summing node at the inverting input is called a virtual ground. Which description best captures what “virtual ground” means in terms…

Accepted Answer

Introduction / Context:The phrase “virtual ground” is used constantly when analyzing inverting op-amp circuits. Students often misinterpret it as a literal ground connection that can sink or source current. In reality, it is “virtual” only in voltage, not in current-handling capability. This question confirms the correct, practical meaning so you can size feedback networks and return paths correctly. Given Data / Assumptions: Ideal op-amp with very high open-loop gain and negligible input bias current. Negative feedback forces the inverting input to follow the noninverting input's voltage. In a textbook inverting amplifier, the noninverting input is tied to ground (0 V reference). Concept / Approach:With negative feedback, the op-amp drives its output until v− ≈ v+ (the “golden rule”). If v+ is grounded, the inverting node sits at approximately 0 V, hence “virtual ground.” However, that node is not a physical return capable of carrying arbitrary current. Ideally, no current flows into the op-amp input; instead, the current arriving through the input resistor leaves through the feedback path and ultimately returns to the real ground via the source and supply rails. Step-by-Step Solution: Recognize: v+ = 0 V → feedback makes v− ≈ 0 V (virtual ground in voltage).Apply KCL at the summing node: i_in ≈ i_fb because i_opamp_in ≈ 0 A.Conclude: the node is near 0 V but is not a current sink/source; currents circulate through the feedback network and supply returns.Therefore, the best description is “0 V in potential but not a power ground.” Verification / Alternative check:Simulate an inverting amplifier: measuring node voltage shows ~0 V while op-amp input current remains near zero. If you attempt to draw load current from the summing node, the amplifier saturates or behaves incorrectly, proving it is not a power return. Why Other Options Are Wrong: True chassis ground: incorrect—no direct low-impedance connection to the return plane exists at the summing node.Floating/undefined: false—the node voltage is well-defined by feedback.Exactly 0 V and perfect return: unrealistic; exact equality requires infinite gain, and current-sinking ability is absent.Forces supply currents: misunderstanding; supply currents are determined by output drive, not by “equal and opposite” at the node. Common Pitfalls:Attempting to connect loads to the virtual ground node; ignoring finite open-loop gain and input bias currents; forgetting that “virtual” denotes approximate voltage equality, not current capability. Final Answer:Approximately 0 V in potential, but it cannot source or sink load current like a real ground

Question 4

Op-amp summing node currents — does current flow “into” a virtual ground? Consider the inverting-input summing node of an op-amp with negative feedback. What correctly describes the current at that node?

Accepted Answer

Introduction / Context:Students sometimes think a “virtual ground” is a magical sink for current. In ideal op-amp analysis, input bias currents are approximately zero, so KCL at the summing node tells us that currents arriving via input resistors leave via the feedback network, not into the op-amp input pin. This clarifies how inverting gain equations are derived and why the op-amp input node must not be used as a power return. Given Data / Assumptions: Ideal op-amp behavior: infinite input impedance, zero input current. Negative feedback keeps the inverting node at approximately the noninverting input voltage. Linear operation (no saturation). Concept / Approach:At the summing junction, KCL applies: the algebraic sum of currents is zero. With i_in− ≈ 0 A, the current through each input resistor is balanced by the current through the feedback path. The node voltage being near 0 V does not imply the node can accept arbitrary current; it merely simplifies the gain relationship v_out = −(Rf/Rin)*v_in for the inverting stage. Step-by-Step Solution: Assume i_in− ≈ 0 A (ideal).Write KCL: Σ currents through input resistors + current through feedback = 0.Solve for v_out using v_node ≈ 0 V: v_out = −(Rf/Rin) * v_in.Interpretation: currents circulate in external components, not into the op-amp input. Verification / Alternative check:Measure input bias in datasheets (nA to pA). SPICE shows node current into the input terminal is orders of magnitude smaller than through Rin and Rf. Therefore, practical designs account for tiny bias only in precision applications (add bias-cancellation resistors). Why Other Options Are Wrong: Significant absorption by the op-amp: contradicts high input impedance.Instant return through ground pin: misrepresents current paths.No current can pass: wrong—currents pass through the resistors; the node obeys KCL.Equal currents into both inputs: not how differential inputs operate in linear mode. Common Pitfalls:Using the summing node as a return for other circuits; neglecting bias current errors in precision designs; ignoring finite open-loop gain which makes the node only approximately at 0 V. Final Answer:Branch currents enter and leave the node through resistors, but essentially none flows into the op-amp input terminal

Question 5

Op-amp feedback fault — effect of an open feedback resistor: In a standard inverting or noninverting op-amp amplifier, what typically happens if the feedback resistor path opens during operation?

Accepted Answer

Introduction / Context:Negative feedback stabilizes gain, linearity, and bandwidth in op-amp amplifiers. A failure in the feedback path removes this control, returning the op-amp to near open-loop behavior with huge gain and rail-to-rail saturation for even tiny input offsets. Recognizing this failure mode accelerates troubleshooting. Given Data / Assumptions: Voltage-feedback op-amp with resistive feedback network. Supply rails are finite (e.g., ±15 V or single-supply). Small input offsets/noise always exist. Concept / Approach:Open feedback means the op-amp no longer compares its inputs in a controlled loop. With open-loop gain typically 10^5 to 10^6, microvolt-level input differences can drive the output to a rail. The result is severe clipping when a signal is applied, or a DC-saturated output in quiescent conditions. Protection or muting is not intrinsic unless extra circuitry is provided. Step-by-Step Solution: Model feedback path open → loop gain ≈ 0.Open-loop gain remains huge → tiny input error produces rail output.Applied signals appear severely distorted or fully clipped.Therefore, expect saturation/clipping, not gentle gain change. Verification / Alternative check:Bench test: lift Rf in an inverting amplifier. The output jumps to a rail. Reconnecting Rf restores linear operation and the designed closed-loop gain. Why Other Options Are Wrong: Unity-gain glide: wrong—removing Rf does not create a unity follower.Auto-mute: op-amps do not mute unless externally designed to.Phase margin improvement: irrelevant to the primary failure symptom.Only bias change: effects are far larger than bias-current tweaks. Common Pitfalls:Mistaking a broken feedback trace for a fried op-amp; overlooking solder cracks on Rf; assuming the device is faulty when the loop is actually open. Final Answer:The amplifier loses negative feedback and the output saturates or clips severely

Question 6

Digital fundamentals — latch/flip-flop taxonomy: Is an S–R (Set–Reset) flip-flop an example of a bistable multivibrator circuit?

Accepted Answer

Introduction / Context:Multivibrators are classified by the number of stable states: bistable (two stable states), monostable (one stable state), and astable (no stable state). The S–R flip-flop is a foundational storage element in digital electronics and is the canonical example of a bistable device. Given Data / Assumptions: S–R flip-flop implemented with cross-coupled gates or latches. Two stable outputs: Q = 0 or Q = 1. External inputs can set or reset the state. Concept / Approach:A bistable multivibrator remains indefinitely in its current state until an input causes a transition to the other state. The S input forces Q to 1 (set), and the R input forces Q to 0 (reset), subject to implementation details and invalid combinations (e.g., S = R = 1 in simple NOR-latch forms). This persistent storage is why the S–R flip-flop is used as a memory element. Step-by-Step Solution: Identify device type: two stable equilibria (Q = 0, Q = 1).Show persistence: state holds without continuous stimulation.Inputs trigger transitions: S sets, R resets.Therefore, it is bistable by definition. Verification / Alternative check:Truth tables and timing diagrams of S–R latches and flip-flops demonstrate two stable states and edge/level-triggered control. Datasheets list these as bistable elements. Why Other Options Are Wrong: Monostable/astable claims contradict the two-stable-state behavior.Op-amp versus logic: implementation technology does not change its bistable nature.Asynchronous versus synchronous: both are bistable; the difference is in timing control. Common Pitfalls:Confusing “latch” (level-sensitive) with “flip-flop” (edge-triggered); ignoring invalid input conditions in simple S–R latch implementations. Final Answer:Yes, an S–R flip-flop is a bistable multivibrator

Question 7

Crystal oscillators — dependence of frequency: For a quartz crystal used in oscillators, what primarily sets the oscillation frequency under normal operating conditions?

Accepted Answer

Introduction / Context:Quartz crystals are precision frequency-determining elements. New learners sometimes assume that increasing the applied voltage changes frequency the way a motor speeds up with more voltage. In reality, a crystal’s frequency is set by its mechanical resonance and the surrounding network, while the drive level mainly affects amplitude and long-term aging if excessive. Given Data / Assumptions: Pierce/Colpitts-style crystal oscillator or clock generator. Proper biasing so the crystal operates in its linear region (specified drive level). Stable temperature and supply conditions. Concept / Approach:A crystal behaves like a very high-Q resonator with motional L, C, and R. Its series and parallel resonant frequencies are determined by cut and geometry. The external load capacitance slightly “pulls” the parallel-resonant frequency. Drive voltage primarily influences oscillation amplitude and can cause nonideal effects (nonlinearities, aging) if excessive, but it does not intentionally tune frequency over a wide range. Step-by-Step Solution: Identify the resonant model: motional parameters set f_s and f_p.Recognize load capacitance pulling: small, predictable shifts by changing C_load.Note drive level: keep within datasheet limits to avoid aging and spurious modes.Conclude: frequency depends on resonance and load capacitance, not applied voltage amplitude. Verification / Alternative check:Datasheets specify load capacitance for target frequency (e.g., 18 pF) and give tight tolerance and temperature coefficients. No “voltage-to-frequency” spec exists for normal operation beyond small, unintended shifts. Why Other Options Are Wrong: Voltage-dependent frequency: crystals are not voltage-controlled oscillators.DC bias polarity: crystals are AC devices; DC has negligible intended effect.Magnetic field/package color: irrelevant for frequency setting. Common Pitfalls:Confusing VCOs (varactor-tuned) with crystals; ignoring the specified load capacitance; overdriving the crystal and causing reliability issues. Final Answer:The crystal’s mechanical resonance (cut, dimensions) and the external load capacitance, not the drive voltage amplitude

Question 8

Differential amplifier behavior — equal inputs: If the two inputs of an ideal differential amplifier are exactly equal in magnitude and phase, what is the expected output?

Accepted Answer

Introduction / Context:A differential amplifier amplifies the difference between its inputs and rejects common-mode signals (those that are the same at both inputs). This question tests recognition of the ideal response and sets the stage for understanding CMRR in practical devices. Given Data / Assumptions: Ideal differential amplifier behavior. Both inputs receive exactly the same signal. Linear operation (no saturation). Concept / Approach:The differential gain A_d multiplies (v2 − v1). If v1 = v2, then (v2 − v1) = 0 and the ideal output is zero. Real amplifiers have a finite common-mode gain A_cm, so the output is not perfectly zero, but the ratio CMRR = A_d / A_cm is designed to be very large, making the residual output tiny. Step-by-Step Solution: Write v_out = A_d * (v2 − v1) + A_cm * v_cm.Set v1 = v2 → differential term is zero.For an ideal amp, A_cm = 0 → v_out = 0 V.Therefore, the expected output is ideally zero. Verification / Alternative check:Instrumentation amplifiers specify CMRR figures (e.g., 100 dB), indicating very strong rejection of equal inputs. Lab tests show a small residual due to finite CMRR, input mismatch, and offset. Why Other Options Are Wrong: “Twice the input”: that is summing, not differencing.Inverted same magnitude: describes single-ended inverting gain, not differential equal-input case.Clipped or random: unrelated to ideal differential operation. Common Pitfalls:Assuming any input produces output; forgetting that equal inputs cancel; ignoring that CMRR is finite in practice. Final Answer:Ideally zero output due to common-mode rejection

Question 9

Inverting input drive — output polarity: When an input signal is applied to the inverting input of an op-amp and the noninverting input is grounded, what is the polarity of the output relative to the input (within the linear range)?

Accepted Answer

Introduction / Context:The inverting op-amp configuration is one of the first linear circuits taught. Its hallmark is a 180-degree phase inversion between input and output. Recognizing this helps when chaining stages, summing signals, or designing active filters with correct phase response. Given Data / Assumptions: Ideal op-amp with negative feedback. Noninverting input tied to ground reference. Signal applied through an input resistor to the inverting input. Concept / Approach:With the noninverting input at 0 V, feedback keeps the inverting input near 0 V (virtual ground). The closed-loop gain is −Rf/Rin, a negative value indicating inversion. Thus, a positive input produces a negative output, and vice versa, until limited by the supply rails. Step-by-Step Solution: Write v_out = −(Rf/Rin) * v_in.Note the negative sign → 180-degree inversion.Magnitude determined by |Rf/Rin|; ensure |v_out| stays within rails.Therefore, output is opposite in polarity to the input. Verification / Alternative check:Oscilloscope shows input and output sinusoidal waveforms inverted by half a cycle with amplitude ratio equal to |Rf/Rin|. Step response also inverts polarity instantly, within slew limits. Why Other Options Are Wrong: Same polarity: describes noninverting configuration.No output: incorrect—grounding the noninverting input is normal for inverting stages.Random/clipped: not intrinsic unless overdriven or poorly biased. Common Pitfalls:Ignoring output swing limits; forgetting to include input bias cancellation when using large resistances; miswiring Rin and Rf leading to positive feedback. Final Answer:Opposite polarity (inverted) with magnitude set by the closed-loop gain

Question 10

Multivibrator types — triggering requirement: A monostable multivibrator (one-shot) exhibits which operating characteristic?

Accepted Answer

Introduction / Context:Monostable, astable, and bistable multivibrators serve different timing and storage roles. The monostable (one-shot) is used to generate a single pulse of defined width when triggered, making it fundamental in timing, debounce, and pulse-stretch applications. Given Data / Assumptions: Standard one-shot using logic, op-amp comparators, or dedicated ICs (e.g., 555 in monostable mode). Defined timing components (R and C) set pulse width. Clean triggering edge is provided. Concept / Approach:A monostable has one stable state. Upon receiving a trigger, it transitions to a quasi-stable state for a duration T set by circuit parameters, then automatically returns to the stable state. It does not free-run. Bistable devices, by contrast, require inputs to change state and remain there until commanded; astables free-run between states with no stable resting state. Step-by-Step Solution: Identify: only one stable state → needs a trigger to leave it.Trigger received → output pulse of duration T (e.g., T ≈ 1.1 * R * C in 555).After T, circuit returns to its stable state automatically.Thus, the defining trait is the need for an external trigger. Verification / Alternative check:Scope measurements show a single pulse following each trigger edge; with no triggers, the output remains in its stable level indefinitely. Why Other Options Are Wrong: Continuous oscillation: describes an astable, not a monostable.Two stable states: that is a bistable (flip-flop).DC–AC conversion/duty claims: unrelated to the definition.Cannot be implemented with logic: false—one-shots exist as standard logic functions and as 555 timers. Common Pitfalls:Confusing retriggerable vs non-retriggerable modes; ignoring input conditioning and debounce for clean triggering; miscalculating pulse width due to component tolerances. Final Answer:It requires an external trigger to enter a temporary quasi-stable state before returning to its stable state

Question 11

Comparators with hysteresis — terminology: In a Schmitt trigger, what is the correct name for the difference between the upper trigger point (UTP) and lower trigger point (LTP)?

Accepted Answer

Introduction / Context:A Schmitt trigger is a comparator with positive feedback that introduces two distinct switching thresholds to reject noise and provide clean transitions. The gap between these thresholds is a key specification that directly influences noise immunity and input sensitivity. Given Data / Assumptions: Non-inverting or inverting Schmitt trigger configuration. Defined UTP and LTP dependent on resistor ratios and reference levels. Slowly varying or noisy input signal requiring clean switching. Concept / Approach:Because of positive feedback, the input must exceed an upper threshold to switch one way and fall below a lower threshold to switch back. The numerical difference UTP − LTP is called hysteresis (or hysteresis width). The term “Schmitt trigger” is the name of the circuit topology, not the difference itself. Step-by-Step Solution: Define thresholds: UTP for rising input, LTP for falling input.Compute the difference: ΔV = UTP − LTP.Name ΔV properly: hysteresis width.Relate ΔV to noise rejection: larger ΔV → greater immunity. Verification / Alternative check:Datasheets specify hysteresis in volts and provide formulas for UTP/LTP in terms of resistor ratios and reference levels. Lab tests show clean transitions even with noise when hysteresis is present. Why Other Options Are Wrong: Calling the difference “the Schmitt trigger” confuses the device with its parameter.Propagation delay: time metric, not a threshold gap.Bias margin/metastability window: different concepts in digital design. Common Pitfalls:Mislabeling thresholds; forgetting that hysteresis introduces memory; using too little hysteresis causing chatter at the switching point. Final Answer:Hysteresis (also called hysteresis width or threshold band)

Question 12

Pin functions — classic 741 op-amp (8-pin DIP): For the standard μA741/LM741 op-amp in an 8-pin dual-in-line package, which pin number is the inverting (−) input?

Accepted Answer

Introduction / Context:Knowing pin assignments prevents wiring errors that can cause oscillation, inversion mistakes, or device damage. The 741 is a classic teaching op-amp; despite newer devices, its pinout remains a reference pattern for many DIP-8 op-amps. Given Data / Assumptions: Device: 741-family op-amp in 8-pin dual-in-line (DIP) package. Standard orientation notch indicates pins counterclockwise from top-left as 1–4 and 5–8. Typical supply rails on pins 4 (−V) and 7 (+V). Concept / Approach:The textbook 741 pinout is: 1 = offset null, 2 = inverting input, 3 = noninverting input, 4 = −V, 5 = offset null, 6 = output, 7 = +V, 8 = NC. Thus, the inverting input is pin 2 and the noninverting input is pin 3. Other op-amps may differ (especially single-supply or rail-to-rail types), so always check the datasheet. Step-by-Step Solution: Orient package, identify notch/dot to locate pin 1.Recall mapping: pin 2 → inverting input; pin 3 → noninverting input.Confirm supply pins: 7 = +V, 4 = −V; output at pin 6.Answer: inverting input is pin 2. Verification / Alternative check:Cross-check any 741 datasheet or lab bench component; continuity from pin 2 to inverting input circuitry confirms the assignment. Why Other Options Are Wrong: Pin 3 is the noninverting input.Pin 6 is the output.Pin 7 is +V supply; pin 4 is −V supply. Common Pitfalls:Mirroring pin numbers when flipping the IC; confusing SOIC pinouts with DIP; assuming all op-amps share the 741 pinout without checking. Final Answer:Pin 2 is the inverting (−) input

Question 13

Voltage follower (unity-gain buffer) using an operational amplifier: In a classic voltage-follower configuration, is the op-amp output node connected directly to the inverting (−) input while the non-inverting (+) input serves as the signal input?

Accepted Answer

Introduction / Context:A voltage follower, also called a unity-gain buffer, is a fundamental operational-amplifier configuration. It provides a gain of approximately 1 while offering very high input impedance and very low output impedance. The question checks whether you remember the exact feedback connection used to realize this behavior. Given Data / Assumptions: Single op-amp operated in linear (closed-loop) region. Idealized op-amp assumptions for concept: very large open-loop gain, high input impedance, low output impedance. Feedback is intended to be negative. Concept / Approach:In a unity-gain buffer, the output is fed back directly to the inverting (−) input. The signal is applied to the non-inverting (+) input. With very high open-loop gain A, the closed-loop transfer becomes v_out ≈ v_in because negative feedback forces the differential input v(+) − v(−) toward zero. This gives near-unity gain with excellent impedance buffering. Step-by-Step Solution: Identify topology: connect output to the inverting input (100% negative feedback).Apply a signal to the non-inverting input.Use closed-loop relation: v_out ≈ v_in when the loop is stable and the op-amp remains linear.Conclude: the described wiring is indeed a voltage follower. Verification / Alternative check:Closed-loop gain formula for the non-inverting amplifier with Rf = 0 and Rin → ∞ yields gain = 1. Practical measurements show near-unity gain and strong buffering capability (e.g., driving loads without loading the source). Why Other Options Are Wrong:Incorrect: would imply a different connection than the standard follower. Only correct for ideal op-amps: real op-amps also implement this, with minor non-idealities (offset, bandwidth). AC-coupled only: DC and AC both work; DC accuracy depends on offset and bias currents. Common Pitfalls:Accidentally swapping inputs (causing positive feedback and saturation) or forgetting supply headroom and output swing limits. Final Answer:Correct

Question 14

Active filter identification (op-amp based): A single-op-amp multiple-feedback network using both an input capacitor and a feedback capacitor is commonly used to realize a band-pass response with a center frequency f0 and two cutoffs fL and fH. Base…

Accepted Answer

Introduction / Context:Active filters built around operational amplifiers implement selective frequency responses without inductors. A widely used configuration is the multiple-feedback (MFB) band-pass filter, which uses two capacitors and two resistors around a single op-amp to produce a peak at a chosen center frequency f0 and attenuation at frequencies far below and far above f0. Given Data / Assumptions: Standard single-op-amp MFB topology with one capacitor in the input path and another in the feedback path. Linear operation (no clipping), proper biasing, and stable negative feedback. Defined lower and upper −3 dB corner frequencies fL and fH around a center f0. Concept / Approach:A band-pass filter is defined by a pass region centered at f0 with attenuation below fL and above fH. The MFB design equations set f0, quality factor Q, and midband gain based on the component values. Because the transfer magnitude rises toward f0 and falls away on both sides, the correct classification of this standard op-amp network is “band-pass.” Step-by-Step Solution: Recognize the two-capacitor, two-resistor feedback structure.Recall that its transfer function magnitude peaks at f0.Identify attenuation regions: f ≪ f0 and f ≫ f0 are both suppressed.Conclude the topology implements a band-pass response. Verification / Alternative check:Simulated Bode plots of the MFB filter show a clear midband pass region with slope transitions of approximately +20 dB/dec and −20 dB/dec near the edges for a second-order realization. Why Other Options Are Wrong:Incorrect: contradicts the well-known function of the MFB network. Q = 0.5 only: Q controls selectivity; the response remains band-pass for a wide range of Q values. Dual supplies only: single-supply implementations are common with biasing; filter function is unchanged. Common Pitfalls:Miswiring that flips to positive feedback; forgetting to bias for single-supply operation; loading that alters Q and center frequency. Final Answer:Correct

Question 15

Non-inverting op-amp gain control (clarified without a diagram): For a non-inverting amplifier with input resistor Rin from the inverting input to ground and feedback resistor Rf from output to inverting input, the closed-loop voltage gain is Av = 1…

Accepted Answer

Introduction / Context:Without a schematic, it is easy to confuse which resistor controls gain in a non-inverting operational-amplifier stage. This item restates the standard configuration and asks which component change raises the closed-loop voltage gain. The answer relies on the canonical formula for the non-inverting gain. Given Data / Assumptions: Non-inverting op-amp: input applied to the + node. Feedback network: Rf from output to − input, Rin from − input to ground. Closed-loop gain Av = 1 + (Rf / Rin), ideal op-amp behavior assumed. Concept / Approach:Because Av depends on the ratio Rf / Rin, the gain increases if Rf increases or if Rin decreases. Changing the input signal amplitude does not change the gain; it only changes output level proportionally. Scaling Rf and Rin together by the same factor leaves the ratio unchanged, so Av stays the same. Step-by-Step Solution: Start with Av = 1 + (Rf / Rin).Consider option A: decreasing Rin makes Rf / Rin larger ⇒ Av increases.Consider option B: increasing Rf makes Rf / Rin larger ⇒ Av increases.Options C and D: input amplitude and equal scaling of both resistors do not change Av. Verification / Alternative check:Pick numerical values (e.g., Rf = 90 kΩ, Rin = 10 kΩ → Av = 10). Double Rf to 180 kΩ → Av = 19; halve Rin to 5 kΩ → Av = 19. The gain rises in both cases. Why Other Options Are Wrong:Decrease Rin: would also be correct in principle, but this option is not listed as the answer; however, increasing Rf is a direct, unambiguous method selected as correct here. Increase input amplitude: changes output level but not the gain setting. Decrease both by the same factor: ratio unchanged, so gain unchanged. Common Pitfalls:Confusing inverting vs non-inverting formulas; ignoring how bias currents and noise may influence practical component choices. Final Answer:Increase Rf while keeping Rin constant

Question 16

Common-mode rejection ratio (CMRR) for operational amplifiers: CMRR is defined as the ratio of which two quantities?

Accepted Answer

Introduction / Context:Operational amplifiers are designed to amplify the difference between their two inputs while rejecting any signal common to both. The figure of merit that quantifies this ability is the common-mode rejection ratio (CMRR), typically expressed in decibels for convenience. Given Data / Assumptions: Linear operation of the op-amp around its operating point. Differential-mode gain Ad is much larger than common-mode gain Acm in good designs. Voltages used for gain definitions (not power). Concept / Approach:By definition, CMRR = Ad / Acm, where Ad is the differential voltage gain and Acm is the common-mode voltage gain. In dB form, CMRR_dB = 20 * log10(Ad / Acm). High CMRR indicates excellent rejection of common-mode interference such as hum or coupled noise appearing equally on both inputs. Step-by-Step Solution: Identify Ad: gain from v(+) − v(−) to output.Identify Acm: gain from the average/common input to output.Form the ratio: CMRR = Ad / Acm.Convert to dB if needed: 20 * log10(CMRR). Verification / Alternative check:Datasheets provide typical and minimum CMRR values (e.g., 80 dB to 120 dB) measured over specified frequencies and supply conditions, confirming the voltage-gain-based definition. Why Other Options Are Wrong:Differential/common power gains: power terminology is not used for CMRR definition. Ideal to actual gain: unrelated; that would describe bandwidth or open-loop vs closed-loop differences. Signal to noise: a different metric (signal-to-noise ratio), not CMRR. Common Pitfalls:Confusing CMRR with PSRR (power-supply rejection ratio) or with input common-mode range; mixing voltage and power terms. Final Answer:the differential voltage gain, the common-mode voltage gain

Question 17

Non-inverting amplifier sizing (numerical): A non-inverting op-amp has a closed-loop gain Av = 10. What input voltage is required to obtain an output of 3.43 V (assume linear operation and no saturation)?

Accepted Answer

Introduction / Context:Non-inverting op-amp stages are common whenever a designer needs a precise, positive gain with high input impedance. Sizing the input for a desired output is a straightforward application of the closed-loop gain formula. This problem reinforces the relationship between output, gain, and input amplitude. Given Data / Assumptions: Closed-loop gain Av = 10 (dimensionless voltage gain). Desired output Vout = 3.43 V. Linear region of operation: the op-amp is properly powered and not saturating. Concept / Approach:For a non-inverting amplifier, Vout = Av * Vin. Therefore, the input required is Vin = Vout / Av. With Av fixed at 10, this is a single-step division. The options are in millivolts to encourage correct unit handling. Step-by-Step Solution: Write the relationship: Vout = Av * Vin.Solve for Vin: Vin = Vout / Av = 3.43 V / 10.Compute: Vin = 0.343 V = 343 mV.Select the matching choice: 343 mV. Verification / Alternative check:Back-calculate: 343 mV * 10 = 3.43 V, confirming the arithmetic and units. Why Other Options Are Wrong:400 mV, 480 mV, 600 mV produce outputs of 4.00 V, 4.80 V, and 6.00 V respectively at Av = 10, which do not match the target 3.43 V. Common Pitfalls:Mixing up Av = 1 + (Rf/Rin) with the direct scaling Vout = Av * Vin; forgetting to convert between volts and millivolts; ignoring headroom limits which can matter in real hardware but do not affect this arithmetic. Final Answer:343 mV

Question 18

Quartz crystal resonator quality factor: Compared to most L–C networks, the Q (quality factor) of a quartz crystal is typically _____.

Accepted Answer

Introduction / Context:Quartz crystals are used in oscillators and filters because they provide very stable frequencies and narrow bandwidths. The measure that captures this sharpness of resonance is the quality factor, Q. Crystals have Q values far exceeding those of simple lumped L–C tanks at comparable frequencies. Given Data / Assumptions: Piezoelectric quartz resonator operated near its series or parallel resonance. Small-signal, linear regime, typical for timing applications. Ambient conditions where aging and temperature drift are not the focus. Concept / Approach:Q is defined as 2 * pi * (energy stored per cycle) / (energy dissipated per cycle) and equivalently as f0 / BW for narrowband resonators. Quartz exhibits extremely low loss, so its Q can reach 10^4 to 10^6 depending on cut and frequency, vastly higher than L–C realizations with discrete inductors and capacitors at similar frequencies. Step-by-Step Solution: Recall typical L–C Q values (tens to a few hundred) versus crystal Q (thousands to a million).Relate high Q to narrow bandwidth and stable oscillation frequency.Match the description “extremely high” to crystal behavior.Select the correct option. Verification / Alternative check:Manufacturer datasheets and oscillator design texts list loaded Q values many orders of magnitude above simple L–C tanks, confirming the qualitative statement. Why Other Options Are Wrong:Extremely low / less than 10 / ≈ 40: far below observed crystal Q; would lead to very broad, unstable resonance inconsistent with crystal performance. Common Pitfalls:Confusing Q with frequency stability metrics like ppm drift; while related in effect, they are distinct specifications. Final Answer:extremely high

Question 19

Ideal operational amplifier properties (concept check): Which of the following is NOT a characteristic of an ideal op-amp?

Accepted Answer

Introduction / Context:Ideal op-amp assumptions simplify circuit analysis: infinite open-loop gain, infinite input impedance, zero output impedance, and infinite bandwidth (among others). This question asks which listed attribute does not belong to the idealized set and therefore must be rejected. Given Data / Assumptions: Ideal op-amp model used in linear circuit analysis. Open-loop gain A → ∞, input currents ≈ 0, output behaves like an ideal voltage source within limits. Bandwidth considered unbounded for the purpose of the ideal model. Concept / Approach:The idealized op-amp has infinite bandwidth, not “minimum bandwidth.” Infinite bandwidth implies constant gain with zero phase shift for all frequencies of interest. Therefore, among the choices, “Minimum bandwidth” is the property that is NOT consistent with the ideal model and is the correct answer to select as not a characteristic. Step-by-Step Solution: List ideal properties: A → ∞, Rin → ∞, Rout → 0, BW → ∞.Compare each option to the list.Identify mismatch: “Minimum bandwidth”.Select it as the exception. Verification / Alternative check:Any op-amp textbook summarizes the ideal model with infinite bandwidth; the opposite notion of “minimum bandwidth” contradicts that definition. Why Other Options Are Wrong:Infinite voltage gain, infinite input impedance, and zero output impedance are all canonical ideal op-amp traits. Common Pitfalls:Confusing ideal traits with real op-amp limitations (finite GBW, slew rate, output swing). The question explicitly targets the idealized model. Final Answer:Minimum bandwidth

Question 20

Common-mode signals at the inputs of a differential amplifier: A signal is said to be common-mode if the two input nodes see signals with which shared properties?

Accepted Answer

Introduction / Context:Differential amplifiers and op-amps respond primarily to differences between the two inputs. Signals that appear identically on both inputs are called common-mode signals, and good amplifiers reject them to minimize interference and noise transmission. Given Data / Assumptions: Both inputs are driven by the same time-varying waveform. Definitions are in the voltage domain. Amplifier is linear around its operating point. Concept / Approach:A common-mode signal is identical at the two inputs in amplitude, phase, and frequency (and ideally in waveform shape). Because the amplifier ideally amplifies only the difference v(+) − v(−), such a shared signal should produce no output in the ideal case. Real devices have finite CMRR, so a small residual output can occur. Step-by-Step Solution: Define v_cm(t) applied to both inputs equally.Note that identical amplitude, phase, and frequency characterize “same signal”.Conclude: all three properties are shared for common-mode signals.Select “All of the above”. Verification / Alternative check:CMRR tests inject the same sinusoid (same amplitude, phase, frequency) on both inputs and measure the small output; this matches the definition used by manufacturers. Why Other Options Are Wrong:Picking only one property is incomplete; all listed properties must match to be truly common-mode. Common Pitfalls:Confusing common-mode with differential-mode; assuming frequency alone defines common-mode without checking amplitude and phase equality. Final Answer:All of the above

Operational Amplifiers Questions