Question 1

Hexadecimal decoder input width: does a hexadecimal (1-of-16) decoder select one of sixteen outputs based on an 8-bit binary input?

Accepted Answer

Introduction / Context: Hexadecimal decoders are common in address decoding and display drivers. A “hex” quantity spans sixteen distinct symbols (0–F), which directly maps to 4 bits of binary information. The question probes whether such a decoder requires 8-bit inputs. Given Data / Assumptions: Hexadecimal implies 16 distinct codes. Binary representation uses 4 bits for 16 states. One-of-16 output selection is assumed. Concept / Approach: Because 2^4 = 16, only 4 input bits are needed to uniquely select one of 16 outputs. An 8-bit input would encode 256 states, vastly exceeding the 16 outputs of a basic hexadecimal decoder. Some devices may include enables or polarity options, but the main data input width for hex selection is 4 bits. Step-by-Step Solution: 1) Compute required width: m outputs need log2(m) input bits.2) For m = 16, log2(16) = 4, so four inputs are sufficient.3) Therefore, 8-bit input is not required for a 1-of-16 decoder.4) Conclude the statement is incorrect. Verification / Alternative check: Datasheets for 4-to-16 decoders (e.g., 74HC154) specify four address inputs A–D and sixteen outputs. Why Other Options Are Wrong: Applies: misstates the necessary input width. BCD and extra enables do not change that 4 bits encode 16 states; enables gate functionality but are not primary address bits. Common Pitfalls: Confusing “hexadecimal display decoder” (which may include segment mapping) with the address-width requirement; conflating control lines with data width. Final Answer: Does not apply

Question 2

MUX select-line count: for a sixteen-input (16-to-1) multiplexer, how many data-select control lines are required to address all inputs?

Accepted Answer

Introduction / Context: Select-line count is a fundamental sizing rule for multiplexers. A 16-to-1 MUX forwards one of sixteen inputs to the output, so the number of address lines must be sufficient to encode sixteen distinct choices. This question reinforces the log2 relationship used throughout digital design. Given Data / Assumptions: The device is a single 16-to-1 multiplexer. Binary addressing is used for the select lines. Optional enable pins do not replace address bits. Concept / Approach: With M inputs, the number of select lines s must satisfy 2^s ≥ M. For M = 16, 2^4 = 16, so s = 4. Fewer than four lines cannot uniquely address all inputs; more than four would be redundant for basic selection, though sometimes extra lines exist for hierarchical selection or banking. Step-by-Step Solution: 1) Set 2^s = 16 → s = 4.2) Confirm that codes 0000 through 1111 map to inputs D0…D15.3) Recognize that enables are orthogonal to select-line count.4) Conclude four select lines are required. Verification / Alternative check: Commercial 16:1 MUXes (e.g., 74HC4067 analog MUX) use four address lines S0–S3 to select channels 0–15. Why Other Options Are Wrong: Two or three lines: 2^2 = 4 and 2^3 = 8, insufficient. Five lines: 2^5 = 32, more than needed for 16 inputs. Common Pitfalls: Counting enable pins as address lines; mixing up multiplexer and decoder sizing. Final Answer: Four select lines

Combinational Logic Circuits Questions