Introduction / Context:
In power electronics and triggering circuits, the Silicon Unilateral Switch (SUS) is a small-signal thyristor-like device used to generate a precise pulse when its breakover condition is met. Understanding its internal construction helps distinguish it from SCRs, UJTs, and PUTs.
Given Data / Assumptions:
- SUS provides unilateral triggering at a preset breakover voltage.
- Comparison is with SCR, UJT, and PUT.
- Focus is on internal structure and functional equivalence.
Concept / Approach:The SUS can be modeled functionally as a PUT combined with a built-in avalanche reference path. This arrangement establishes a repeatable trigger point without external zeners or elaborate biasing.
Step-by-Step Solution:1) SUS goal: produce a sharp trigger when V reaches a designed breakover.2) PUT alone needs external biasing; adding an avalanche diode between gate–cathode sets a reference.3) When anode–cathode voltage and gate conditions satisfy breakover, the device snaps on unilaterally.4) Hence, a practical equivalence is “PUT + avalanche diode (anti-parallel across gate–cathode)”.Verification / Alternative check:Datasheets often state SUS as a PUT derivative with an integral avalanche junction to establish V_BO precisely. That differentiates it from an SCR (power switch) or UJT (two-layer device with emitter injection behavior).
Why Other Options Are Wrong:- Exactly similar to an SCR: incorrect; SCR is a power device with different structure and bilateral gate physics.
- Similar to a UJT: incorrect; SUS behaves closer to PUT than UJT.
- SCR + avalanche diode in parallel: not the way SUS is realized; parallel across anode–cathode is not the SUS reference path.
- None of the above: incorrect because the correct construction is known.
Common Pitfalls:- Confusing SCR family devices; SUS is low-power triggering, not a high-power controller.
- Thinking the avalanche diode is across anode–cathode instead of gate–cathode.
Final Answer:A PUT with an avalanche diode in anti-parallel between gate–cathode (Option C).
Discussion & Comments