2. In HDL when a circuit is simulated on a computer, the designer must create all the different scenarios that will be experienced by the actual circuit and must also know the proper response to those inputs.
5. In the digital clock project HDL, the 1 pps signal is used as a synchronous clock for all of the counters' stages, which are synchronously cascaded.
7. Top-down design means that we start at the highest level of the hierarchy, or that the entire project is considered to exist in a closed dark box with inputs and outputs.