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Home ‣ Digital Electronics ‣ Programmable Logic Device Comments
  • Question

  • An expensive form of programmable logic is SPLD.


  • Options
  • A. True
  • B. False

  • Correct Answer
  • False 

    • Programmable Logic Device problems

    Search Results

    • 1. Schematic capture is a process performed by PLD software.

    • Options
    • A. True
    • B. False
      • Discuss
    • 2. A PAL consists of an array of fixed AND gates that are connected to a programmable array of OR gates.

    • Options
    • A. True
    • B. False
      • Discuss
    • 3. A GAL is a programmable/reprogrammable PAL.

    • Options
    • A. True
    • B. False
      • Discuss
    • 4. The JTAG signals are named TDI, TDO, TMS, and TCK.

    • Options
    • A. True
    • B. False
      • Discuss
    • 5. VHDL code is divided into three sections: library declaration, entity declaration, and architecture body.

    • Options
    • A. True
    • B. False
      • Discuss
    • 6. The GAL16V8 has eight dedicated input pins.

    • Options
    • A. True
    • B. False
      • Discuss
    • 7. PLDs did not gain widespread acceptance with digital until the mid-1980s, when a device called a PAL was introduced.

    • Options
    • A. True
    • B. False
      • Discuss
    • 8. In the FLEX10K device, the LE can produce two outputs to drive local (LAB) and global (fast track) interconnects on the chip.

    • Options
    • A. True
    • B. False
      • Discuss
    • 9. Xilinx software uses triangular symbols called buffers to define pins as input or output.

    • Options
    • A. True
    • B. False
      • Discuss
    • 10. The architecture of a PAL differs slightly from that of a PROM.

    • Options
    • A. True
    • B. False
      • Discuss

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