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  • Question
  • Assume a 4-bit Johnson counter is initially cleared. After the first clock pulse the output is 0001. After the next clock pulse the output will be ________.


  • Options
  • A. 0011
  • B. 0010
  • C. 1000
  • D. 0110

  • Correct Answer
  • 0011 


  • Shift Registers problems


    Search Results


    • 1. A 4-bit ring counter is loaded with a single 1. The frequency of any given output is ________.

    • Options
    • A. the same as the clock
    • B. twice the clock frequency
    • C. one-half the clock frequency
    • D. one-fourth the clock frequency
    • Discuss
    • 2. Assume a LOW logic level is placed on the SHIFT/LOAD input of a 74195 shift register. The output will change ________.

    • Options
    • A. immediately
    • B. if the CLOCK is also LOW
    • C. on the next clock leading edge
    • D. depending on the J and K inputs
    • Discuss
    • 3. A Johnson counter, constructed with N flip-flops, has how many unique states?

    • Options
    • A. N
    • B. 2N
    • C. 2N
    • D. N2
    • Discuss
    • 4. A type of shift register that requires access to the Q outputs of all stages is ________.

    • Options
    • A. parallel in/serial out
    • B. serial in/parallel out
    • C. serial in/serial out
    • D. a bidirectional shift register
    • Discuss
    • 5. The ring and Johnson shift counters are uncommon circuits that are similar to synchronous counters.

    • Options
    • A. True
    • B. False
    • Discuss
    • 6. A type of shift register in which the Q or Q output of one stage is not connected to the input of the next stage is ________.

    • Options
    • A. parallel in/serial out
    • B. serial in/parallel out
    • C. serial in/serial out
    • D. parallel in/parallel out
    • Discuss
    • 7. An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 µs. The output that has the proper delay is ________.

    • Options
    • A. QE
    • B. QF
    • C. QG
    • D. QH
    • Discuss
    • 8. Assume a 4-bit parallel in/serial out shift register is loaded with a binary number. How many clock pulses are required after the parallel load has occurred before the first bit in the sequence appears on the serial output line?

    • Options
    • A. 0
    • B. 1
    • C. 2
    • D. 3
    • Discuss
    • 9. Shifting a binary number to the left by one position is equivalent to ________.

    • Options
    • A. multiplying by two
    • B. multiplying by four
    • C. dividing by two
    • D. dividing by four
    • Discuss
    • 10. Assume an 8-bit serial in/parallel out shift register needs to be cleared but has no clear input. How many clock cycles are required before a zero applied to the input appears on the QH output?

    • Options
    • A. 1
    • B. 7
    • C. 8
    • D. 9
    • Discuss


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