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Home ‣ Digital Electronics ‣ Logic Gates See What Others Are Saying!
  • Question

  • The gates in this figure are implemented using TTL logic. If the output of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.

    The gates in this figure are implemented using TTL logic. If the output of the inverter is open, and


  • Options
  • A. a steady LOW
  • B. a steady HIGH
  • C. an undefined level
  • D. pulses

  • Correct Answer
  • pulses 

    • More questions

    • 1. A coprocessor is a microprocessor designed with a limited instruction set optimized to perform arithmetic operations very quickly.

    • Options
    • A. True
    • B. False
      • Discuss
    • 2. With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?

    • Options
    • A. 16
    • B. 8
    • C. 4
    • D. 2
      • Discuss
    • 3. Which of the following procedures could be used to check the parallel loading feature of a counter?

    • Options
    • A. Preset the LOAD inputs, set the CLR to its active level, and check to see that the Q outputs match the values preset into the LOAD inputs.
    • B. Apply LOWs to the parallel DATA inputs, pulse the CLK input, and check for LOWs on all the Q outputs.
    • C. Apply HIGHs to all the DATA inputs, pulse the CLK and CLR inputs, and check to be sure that the Q outputs are all LOW.
    • D. Apply HIGHs to all the Q terminals, pulse the CLK, and check to see if the DATA terminals now match the Q outputs.
      • Discuss
    • 4. A one-shot is a special type of multivibrator that must be triggered to produce each output pulse.

    • Options
    • A. True
    • B. False
      • Discuss
    • 5. For a three-input OR gate, with the input waveforms as shown below, which output waveform is correct?


    • Options
    • A. a
    • B. b
    • C. c
    • D. d
      • Discuss
    • 6. When data input I1 of a 74148 octal-to-binary encoder is active, the data output is:

      A0 = 0
      A1 = 0
      A2 = 1


    • Options
    • A. True
    • B. False
      • Discuss
    • 7. Parallel in/parallel out registers have parallel input and output busses.

    • Options
    • A. True
    • B. False
      • Discuss
    • 8. For the inputs shown in the given figure, the output is ________.


    • Options
    • A. 1
    • B. 0 
      • Discuss
    • 9. Simple gate circuits, combinational logic, and transparent S-R flip-flops are synchronous.

    • Options
    • A. True
    • B. False
      • Discuss
    • 10. Solve the network in the figure given below for X.


    • Options
    • A. A + BC + D
    • B. ((A + B)C) + D
    • C. D(A + B + C)
    • D. (AC + BC)D
      • Discuss

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