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  • Question
  • The gates in this figure are implemented using TTL logic. If the output of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.

    The gates in this figure are implemented using TTL logic. If the output of the inverter is open, and


  • Options
  • A. a steady LOW
  • B. a steady HIGH
  • C. an undefined level
  • D. pulses

  • Correct Answer
  • pulses 


  • Logic Gates problems


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    • 1. A NOR gate output is LOW if any of its inputs is LOW.

    • Options
    • A. True
    • B. False
    • Discuss
    • 2. A truth table illustrates how the input level of a gate responds to all the possible output level combinations.

    • Options
    • A. True
    • B. False
    • Discuss
    • 3. A NAND gate output is LOW only if all the inputs are HIGH.

    • Options
    • A. True
    • B. False
    • Discuss
    • 4. A waveform can be enabled or disabled by both AND and OR gates.

    • Options
    • A. True
    • B. False
    • Discuss
    • 5. In a Boolean equation the use of the + symbol represents the OR function.

    • Options
    • A. True
    • B. False
    • Discuss
    • 6. The gates in this figure are implemented using TTL logic. If the output of the inverter has an internal open circuit, what voltage would you expect to measure at the inverter's output?


    • Options
    • A. Less than 0.4 V
    • B. 1.6 V
    • C. Greater than 2.4 V
    • D. All of the above
    • Discuss
    • 7. When does the output of a NOR gate = 0?

    • Options
    • A. Whenever a 0 is present at an input
    • B. Only when all inputs = 0
    • C. Whenever a 1 is present at an input
    • D. Only when all inputs = 1
    • Discuss
    • 8. The gates in this figure are implemented using TTL logic. If the input of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.


    • Options
    • A. a steady LOW
    • B. a steady HIGH
    • C. an undefined level
    • D. pulses
    • Discuss
    • 9. When does the output of a NAND gate = 1?

    • Options
    • A. Whenever a 0 is present at an input
    • B. Only when all inputs = 0
    • C. Whenever a 1 is present at an input
    • D. Only when all inputs = 1
    • Discuss
    • 10. A major advantage of ECL logic over TTL and CMOS is ________.

    • Options
    • A. low power dissipation
    • B. high speed
    • C. both low power dissipation and high speed
    • D. neither low power dissipation nor high speed
    • Discuss


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