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Home ‣ Digital Electronics ‣ Logic Gates Comments
  • Question

  • A truth table illustrates how the input level of a gate responds to all the possible output level combinations.


  • Options
  • A. True
  • B. False

  • Correct Answer
  • False 

    • Logic Gates problems

    Search Results

    • 1. A NAND gate output is LOW only if all the inputs are HIGH.

    • Options
    • A. True
    • B. False
      • Discuss
    • 2. A waveform can be enabled or disabled by both AND and OR gates.

    • Options
    • A. True
    • B. False
      • Discuss
    • 3. In a Boolean equation the use of the + symbol represents the OR function.

    • Options
    • A. True
    • B. False
      • Discuss
    • 4. Power is connected to pins 7 and 14 of a 7408 quad two-input AND gate IC to allow voltage for all four AND gates on the IC.

    • Options
    • A. True
    • B. False
      • Discuss
    • 5. An OR array is programmed by blowing fuses to eliminate selected variables from the output functions.

    • Options
    • A. True
    • B. False
      • Discuss
    • 6. A NOR gate output is LOW if any of its inputs is LOW.

    • Options
    • A. True
    • B. False
      • Discuss
    • 7. The gates in this figure are implemented using TTL logic. If the output of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.


    • Options
    • A. a steady LOW
    • B. a steady HIGH
    • C. an undefined level
    • D. pulses
      • Discuss
    • 8. The gates in this figure are implemented using TTL logic. If the output of the inverter has an internal open circuit, what voltage would you expect to measure at the inverter's output?


    • Options
    • A. Less than 0.4 V
    • B. 1.6 V
    • C. Greater than 2.4 V
    • D. All of the above
      • Discuss
    • 9. When does the output of a NOR gate = 0?

    • Options
    • A. Whenever a 0 is present at an input
    • B. Only when all inputs = 0
    • C. Whenever a 1 is present at an input
    • D. Only when all inputs = 1
      • Discuss
    • 10. The gates in this figure are implemented using TTL logic. If the input of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.


    • Options
    • A. a steady LOW
    • B. a steady HIGH
    • C. an undefined level
    • D. pulses
      • Discuss

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