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- Question
If all inputs to a TTL NAND gate are low, what is the ON, OFF condition of each transistor in the circuit?
Options- A. Q1-ON, Q2-OFF, Q3-ON, Q4-OFF
- B. Q1-ON, Q2-ON, Q3-OFF, Q4-OFF
- C. Q1-OFF, Q2-OFF, Q3-ON, Q4-ON
- D. Q1-OFF, Q2-ON, Q3-OFF, Q4-ON
- Correct Answer
- Q1-ON, Q2-OFF, Q3-ON, Q4-OFF
- 1. Why is a pull-up resistor needed for an open collector gate?
Options- A. to provide Vcc for the IC
- B. to provide ground for the IC
- C. to provide the HIGH voltage
- D. to provide the LOW voltage Discuss
- 2. Ten TTL loads per TTL driver is known as:
Options- A. noise immunity
- B. fan-out
- C. power dissipation
- D. propagation delay Discuss
- 3. The rise time (tr) is the time it takes for a pulse to rise from its ________ point up to its ________ point. The fall time (tf) is the length of time it takes to fall from the ________ to the ________ point.
Options- A. 10%, 90%, 90%, 10%
- B. 90%, 10%, 10%, 90%
- C. 20%, 80%, 80%, 20%
- D. 10%, 70.7%, 70.7%, 10% Discuss
- 4. The most common TTL series ICs are:
Options- A. E-MOSFET
- B. 7400
- C. quad
- D. AC00 Discuss
- 5. The TTL HIGH level source current is higher than the LOW level sinking current.
Options- A. True
- B. False Discuss
- 6. Assume that a particular IC has a supply voltage (Vcc) equal to +5 V and ICCH = 10 mA and ICCL = 23 mA. What is the power dissipation for the chip?
Options- A. 50 mW
- B. 82.5 mW
- C. 115 mW
- D. 165 mW Discuss
- 7. Fan-out is determined by taking the ________ result(s) of ________.
Options- A. smaller,
- B. larger,
- C. smaller,
- D. average,
Discuss
- 8. Why is a pull-up resistor needed when connecting TTL logic to CMOS logic?
Options- A. to increase the output LOW voltage
- B. to decrease the output LOW voltage
- C. to increase the output HIGH voltage
- D. to decrease the output HIGH voltage Discuss
- 9. The output current capability of a single 7400 NAND gate when HIGH is called ________.
Options- A. source current
- B. sink current
- C. IOH
- D. source current of IOH Discuss
- 10. What should be done to unused inputs on TTL gates?
Options- A. They should be left disconnected so as not to produce a load on any of the other circuits and to minimize power loading on the voltage source.
- B. All unused gates should be connected together and tied to V
- C. All unused inputs should be connected to an unused output; this will ensure compatible loading on both the unused inputs and unused outputs.
- D. Unused AND and NAND inputs should be tied to VCC through a 1 kΩ resistor; unused OR and NOR inputs should be grounded. Discuss
Logic Families and Their Characteristics problems
Search Results
Correct Answer: to provide the HIGH voltage
Correct Answer: fan-out
Correct Answer: 10%, 90%, 90%, 10%
Correct Answer: 7400
Correct Answer: False
Correct Answer: 82.5 mW
Correct Answer: smaller,
Correct Answer: to increase the output HIGH voltage
Correct Answer: source current
Correct Answer: Unused AND and NAND inputs should be tied to VCC through a 1 kΩ resistor; unused OR and NOR inputs should be grounded.
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