Timing definition — output change after input change The time interval between a change at a logic input and the corresponding change observed at the output is called:

Introduction / Context:
Every logic gate has finite speed. When an input changes, the output does not respond instantaneously; it changes after a characteristic delay. Understanding and budgeting this delay—propagation delay—is essential for timing closure, avoiding race conditions, and ensuring that synchronous systems meet setup and hold requirements at flip-flop inputs.

Given Data / Assumptions:

• Propagation delay is specified separately for LOW-to-HIGH and HIGH-to-LOW transitions in datasheets.
• Other timing parameters (rise time, fall time, setup/hold) describe different behaviors.
• Noise immunity refers to logic-level noise tolerance, not timing.

Concept / Approach:

Propagation delay (tpd) is measured from a defined input threshold crossing to a defined output threshold crossing. Designers use worst-case tpd in critical-path analysis. In chains of logic, delays add; in asynchronous counters, ripple delays can stack and cause temporary hazards at intermediate outputs.

Step-by-Step Solution:

Verification / Alternative check:

Compare simulation (timing-annotated) vs. lab measurement on an oscilloscope; observed delays align with datasheet tpd values within tolerance.

Why Other Options Are Wrong:

Noise immunity is a DC/noise-level spec; rise time concerns output edge steepness; fan-out is a loading metric; setup time pertains to flip-flop input timing relative to a clock edge.

Common Pitfalls:

Confusing propagation delay with rise/fall time; ignoring temperature/voltage effects on tpd; overlooking the difference between typical and worst-case values.

Final Answer:

propagation delay