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- Question
Which of the following testing procedures uses the JTAG IEEE standard?
Options- A. Bed-of-nails
- B. Flying probe
- C. EXTEST
- D. Boundary scan
- Correct Answer
- Boundary scan
- 1. The Altera MAX 7000 series ________.
Options- A. uses an E2PROM process technology
- B. can have between 2 and 16 LABS and I/O control blocks
- C. is available with DC supply voltages between 2.5 V and 5 V
- D. all of the above Discuss
- 2. Now many times can a GAL be erased and reprogrammed?
Options- A. 0
- B. At least 100
- C. At least 1000
- D. Over 10,000 Discuss
- 3. How many macrocells are in a MAX700S LAB?
Options- A. 8
- B. 16
- C. 32
- D. 64 Discuss
- 4. Which is not a part of a GAL16V8's OLMC?
Options- A. TSMUX
- B. OMUX
- C. FMUX
- D. PSMUX Discuss
- 5. FPGA is the acronym for ________.
Options- A. Flexible Programming [of] Generic Assemblies
- B. Field Programmable Generic Array
- C. Field Programmable Gate Array
- D. Field Programmer's Gate Assembly Discuss
- 6. What is the defining difference between microprocessor/DSP systems and other digital systems?
Options- A. The digital system follows a programmed sequence of instructions that the designer specified.
- B. The microprocessor follows a programmed sequence of instructions that the designer specified.
- C. The digital system is faster.
- D. The microprocessor/DSP is faster. Discuss
- 7. Each programmable array logic (PAL) gate product is applied to an OR gate and, if combinational logic is desired, the product is ORed and then:
Options- A. the polarity fuse is restored
- B. sent to an inverter for output
- C. sent immediately to an output pin
- D. passed to the AND function for output Discuss
- 8. The complex programmable logic device (CPLD) contains several PAL-type simple programmable logic devices (SPLDs) called:
Options- A. macrocells
- B. microcells
- C. AND/OR arrays
- D. fuse-link arrays Discuss
- 9. Which is a mode of operation of the GAL16V8?
Options- A. Simple mode
- B. Complex mode
- C. Registered mode
- D. All of the above Discuss
- 10. The problem of interfacing IC logic families that have different supply voltages (VCC's) can be solved by using a:
Options- A. level-shifter
- B. tristate shifter
- C. decoupling capacitor
- D. pull-down resistor Discuss
Programmable Logic Device problems
Search Results
Correct Answer: all of the above
Correct Answer: At least 100
Correct Answer: 16
Correct Answer: PSMUX
Correct Answer: Field Programmable Gate Array
Correct Answer: The digital system follows a programmed sequence of instructions that the designer specified.
Correct Answer: sent to an inverter for output
Correct Answer: macrocells
Correct Answer: All of the above
Correct Answer: level-shifter
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