Discussion
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- Question
Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
Options- A. input clock pulses are applied only to the first and last stages.
- B. input clock pulses are applied only to the last stage.
- C. input clock pulses are applied simultaneously to each stage.
- D. input clock pulses are not used to activate any of the counter stages.
- Correct Answer
- input clock pulses are applied simultaneously to each stage.
- 1. A principle regarding most display decoders is that when the correct input is present, the related output will switch:
Options- A. HIGH
- B. to high impedance
- C. to an open
- D. LOW Discuss
- 2. A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses?
Options- A. 10002
- B. 10102
- C. 10112
- D. 11012 Discuss
- 3. Once an up-/down-counter begins its count sequence, it cannot be reversed.
Options- A. True
- B. False Discuss
- 4. MOD-6 and MOD-12 counters and multiples are most commonly used as:
Options- A. frequency counters
- B. multiplexed displays
- C. digital clocks
- D. power consumption meters Discuss
- 5. How many different states does a 3-bit asynchronous counter have?
Options- A. 2
- B. 4
- C. 8
- D. 16 Discuss
- 6. What function will the counter shown below be performing during period "B" on the timing diagram?
Options- A. Counting up
- B. Counting down
- C. Inhibited
- D. Loading Discuss
- 7. Any divide-by-N counter can be formed by using external gating to ________ at a predetermined number.
Options- A. HIGH
- B. reset
- C. LOW
- D. preset Discuss
- 8. The terminal count of a modulus-11 binary counter is ________.
Options- A. 1010
- B. 1000
- C. 1001
- D. 1100 Discuss
- 9. Which of the following is an example of a counter with a truncated modulus?
Options- A. 8
- B. 13
- C. 16
- D. 32 Discuss
- 10. Which of the following procedures could be used to check the parallel loading feature of a counter?
Options- A. Preset the LOAD inputs, set the CLR to its active level, and check to see that the Q outputs match the values preset into the LOAD inputs.
- B. Apply LOWs to the parallel DATA inputs, pulse the CLK input, and check for LOWs on all the Q outputs.
- C. Apply HIGHs to all the DATA inputs, pulse the CLK and CLR inputs, and check to be sure that the Q outputs are all LOW.
- D. Apply HIGHs to all the Q terminals, pulse the CLK, and check to see if the DATA terminals now match the Q outputs. Discuss
Counters problems
Search Results
Correct Answer: LOW
Correct Answer: 10002
Correct Answer: False
Correct Answer: digital clocks
Correct Answer: 8
Correct Answer: Counting up
Correct Answer: reset
Correct Answer: 1010
Correct Answer: 13
Correct Answer: Apply LOWs to the parallel DATA inputs, pulse the CLK input, and check for LOWs on all the Q outputs.
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