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Counters
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Question
MOD-6 and MOD-12 counters and multiples are most commonly used as:
Options
A. frequency counters
B. multiplexed displays
C. digital clocks
D. power consumption meters
Correct Answer
digital clocks
Counters problems
Search Results
1. How many different states does a 3-bit asynchronous counter have?
Options
A. 2
B. 4
C. 8
D. 16
Show Answer
Scratch Pad
Discuss
Correct Answer: 8
2. What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop has propagation delays of
t
PHL
= 22 ns and
t
PLH
= 15 ns?
Options
A. 15 ns
B. 22 ns
C. 60 ns
D. 88 ns
Show Answer
Scratch Pad
Discuss
Correct Answer: 88 ns
3. Which is not an example of a truncated modulus?
Options
A. 8
B. 9
C. 11
D. 15
Show Answer
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Discuss
Correct Answer: 8
4. Which of the following statements are true?
Options
A. Asynchronous events do not occur at the same time.
B. Asynchronous events are controlled by a clock.
C. Synchronous events do not need a clock to control them.
D. Only asynchronous events need a control clock.
Show Answer
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Discuss
Correct Answer: Asynchronous events do not occur at the same time.
5. The parallel outputs of a counter circuit represent the:
Options
A. parallel data word
B. clock frequency
C. counter modulus
D. clock count
Show Answer
Scratch Pad
Discuss
Correct Answer: clock count
6. Once an up-/down-counter begins its count sequence, it cannot be reversed.
Options
A. True
B. False
Show Answer
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Discuss
Correct Answer: False
7. A MOD-16 ripple counter is holding the count 1001
2
. What will the count be after 31 clock pulses?
Options
A. 1000
2
B. 1010
2
C. 1011
2
D. 1101
2
Show Answer
Scratch Pad
Discuss
Correct Answer: 1000
2
8. A principle regarding most display decoders is that when the correct input is present, the related output will switch:
Options
A. HIGH
B. to high impedance
C. to an open
D. LOW
Show Answer
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Discuss
Correct Answer: LOW
9. Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
Options
A. input clock pulses are applied only to the first and last stages.
B. input clock pulses are applied only to the last stage.
C. input clock pulses are applied simultaneously to each stage.
D. input clock pulses are not used to activate any of the counter stages.
Show Answer
Scratch Pad
Discuss
Correct Answer: input clock pulses are applied simultaneously to each stage.
10. What function will the counter shown below be performing during period "B" on the timing diagram?
Options
A. Counting up
B. Counting down
C. Inhibited
D. Loading
Show Answer
Scratch Pad
Discuss
Correct Answer: Counting up
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