The final output of a modulus-8 counter occurs one time for every ________. 8 cl

CuriousTab

CuriousTab

Home Aptitude

Discussion

Home ‣ Digital Electronics ‣ Counters Comments

Question
The final output of a modulus-8 counter occurs one time for every ________.
Options
A. 8 clock pulses
B. 16 clock pulses
C. 24 clock pulses
D. 32 clock pulses

Correct Answer

8 clock pulses

Counters problems

Search Results

1. A 22-MHz clock signal is put into a MOD-16 counter. What is the frequency of the Q output of each stage of the counter?
Options
A. Q₁ = 22 MHz, Q₂ = 11 MHz, Q₃ = 5.5 MHz, Q₄ = 2.75 MHz
B. Q₁ = 11 MHz, Q₂ = 5.5 MHz, Q₃ = 2.75 MHz, Q₄ = 1.375 MHz
C. Q₁ = 11 MHz, Q₂ = 11 MHz, Q₃ = 11 MHz, Q₄ = 11 MHz
D. Q₁ = 22 MHz, Q₂ = 22 MHz, Q₃ = 22 MHz, Q₄ = 22 MHz

2. Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.
Options
A. When MR₁ and MR₂ are both HIGH, all Qs will be reset to zero.
B. When MR₁ and MR₂ are both HIGH, all Qs will be reset to one.
C. MR₁ and MR₂ are provided to synchronously reset all four flip-flops.
D. To enable the count mode, MR₁ and MR₂ must be held LOW.

5. What type of register is shown below?
Options
A. Parallel in/parallel out register
B. Serial in/parallel out register
C. Serial/parallel-in parallel-out register
D. Parallel-access shift register

6. How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?
Options
A. 128 gates, 6 inputs to each gate
B. 64 gates, 5 inputs to each gate
C. 64 gates, 6 inputs to each gate
D. 128 gates, 5 inputs to each gate

9. A seven-segment, common-anode LED display is designed for:
Options
A. all cathodes to be wired together
B. one common LED
C. a HIGH to turn off each segment
D. disorientation of segment modules

Comments

More in Digital Electronics: