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Home ‣ Digital Electronics ‣ Flip-Flops Comments
  • Question

  • Which of the following is correct for a gated D flip-flop?


  • Options
  • A. The output toggles if one of the inputs is held HIGH.
  • B. Only one of the inputs can be HIGH at a time.
  • C. The output complement follows the input when enabled.
  • D. Q output follows the input D when the enable is HIGH.

  • Correct Answer
  • Q output follows the input D when the enable is HIGH. 

    • Flip-Flops problems

    Search Results

    • 1. If an input is activated by a signal transition, it is ________.

    • Options
    • A. edge-triggered
    • B. toggle triggered
    • C. clock triggered
    • D. noise triggered
      • Discuss
    • 2. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.

    • Options
    • A. 10.24 kHz
    • B. 5 kHz
    • C. 30.24 kHz
    • D. 15 kHz
      • Discuss
    • 3. One example of the use of an S-R flip-flop is as a(n):

    • Options
    • A. racer
    • B. astable oscillator
    • C. binary storage register
    • D. transition pulse generator
      • Discuss
    • 4. In VHDL, how many inputs will a primitive JK flip-flop have?

    • Options
    • A. 2
    • B. 3
    • C. 4
    • D. 5
      • Discuss
    • 5. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:

    • Options
    • A. edge-detection circuit.
    • B. NOR latch.
    • C. NAND latch.
    • D. pulse-steering circuit.
      • Discuss
    • 6. What is one disadvantage of an S-R flip-flop?

    • Options
    • A. It has no enable input.
    • B. It has an invalid state.
    • C. It has no clock input.
    • D. It has only a single output.
      • Discuss
    • 7. A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?

    • Options
    • A. The power supply is probably noisy.
    • B. The switch contacts are bouncing.
    • C. The socket contacts on the register IC are corroded.
    • D. The register IC is intermittent and failure is imminent.
      • Discuss
    • 8. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:

    • Options
    • A. clock is LOW
    • B. slave is transferring
    • C. flip-flop is reset
    • D. clock is HIGH
      • Discuss
    • 9. The output of a gated S-R flip-flop changes only if the:

    • Options
    • A. flip-flop is set
    • B. control input data has changed
    • C. flip-flop is reset
    • D. input data has no change
      • Discuss
    • 10. The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.

    • Options
    • A. opposite, active clock edge
    • B. inverted, positive clock edge
    • C. quiescent, negative clock edge
    • D. reset, synchronous clock edge
      • Discuss

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