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  • Question
  • An RC circuit used in a nonretriggerable 74121 one-shot has an REXT of 49 kΩ and a CEXT of 0.2 µF. The pulse width (tW) is approximately ________.


  • Options
  • A. 6.9 µs
  • B. 6.9 ms
  • C. 69 ms
  • D. 690 ms

  • Correct Answer
  • 6.9 ms 


  • Flip-Flops problems


    Search Results


    • 1. What is the hold condition of a flip-flop?

    • Options
    • A. both S and R inputs activated
    • B. no active S or R input
    • C. only S is active
    • D. only R is active
    • Discuss
    • 2. In VHDL, how is each instance of a component addressed?

    • Options
    • A. A name followed by a colon and the name of the library primitive
    • B. A name followed by a semicolon and the component type
    • C. A name followed by the library being used
    • D. A name followed by the component library number
    • Discuss
    • 3. An RC circuit used in a 74122 retriggerable one-shot has an REXT of 100 kΩ and a CEXT of 0.005 µF. The pulse width is ________.

    • Options
    • A. 70 µs
    • B. 16 µs
    • C. 160 µs
    • D. 32 µs
    • Discuss
    • 4. The circuit given below fails to function; the inputs are checked with a logic probe and the following indications are obtained: CLK, J1, J2, J3, K1, K2, and K3 are pulsing. Q and are HIGH. and PRE are LOW. What could be causing the problem?


    • Options
    • A. There is no problem.
    • B. The clock should be held HIGH.
    • C. The PRE is stuck LOW.
    • D. The CLR is stuck HIGH.
    • Discuss
    • 5. Why are the S and R inputs of a gated flip-flop said to be synchronous?

    • Options
    • A. They must occur with the gate.
    • B. They occur independent of the gate.
    • Discuss
    • 6. In a 555 timer, three 5 kΩ resistors provide a trigger level of ________.

    • Options
    • A. 1/4 VCC and a threshold level 1/2 VCC
    • B. 1/3 VCC and a threshold level 3/4 VCC
    • C. 1/3 VCC and a threshold level 2/3 VCC
    • D. 1/4 VCC and a threshold level 2/3 VCC
    • Discuss
    • 7. Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?

    • Options
    • A. active-HIGH
    • B. active-LOW
    • Discuss
    • 8. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.

    • Options
    • A. the clock pulse is LOW
    • B. the clock pulse is HIGH
    • C. the clock pulse transitions from LOW to HIGH
    • D. the clock pulse transitions from HIGH to LOW
    • Discuss
    • 9. A 555 operating as a monostable multivibrator has a C1 = 0.01 µF. Determine R1 for a pulse width of 2 ms.

    • Options
    • A. 200 kΩ
    • B. 182 kΩ
    • C. 91 kΩ
    • D. 182 Ω
    • Discuss
    • 10. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________.

    • Options
    • A. 1 kHz
    • B. 2 kHz
    • C. 4 kHz
    • D. 16 kHz
    • Discuss


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