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  • Question
  • Look up the propagation delay from the clock to the output for the 7476. Are the HIGH-to-LOW and LOW-to-HIGH propagation delays the same?


  • Options
  • A. yes
  • B. no, tPLH = 25 ns, tPHL = 40 ns
  • C. no, tPLH = 40 ns, tPHL = 25 ns
  • D. no, tPHL = 25 ns, tPLH = 40 ns

  • Correct Answer
  • no, tPLH = 25 ns, tPHL = 40 ns 


  • Digital Design problems


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    • 1. Why is the Schmitt trigger needed in the 60-Hz TTL-level clock pulse generator?

    • Options
    • A. to provide a triangle wave
    • B. to provide a sine wave
    • C. to provide a rounded pulse waveform
    • D. to provide a sharp pulse waveform
    • Discuss
    • 2. Why would a delay gate be needed for a digital circuit?

    • Options
    • A. A delay gate is never needed.
    • B. to provide for setup times
    • C. to provide for hold times
    • D. to provide for setup times and hold times
    • Discuss
    • 3. A 0.01-µF capacitor is recommended by TTL manufacturers for ________ the power supply.

    • Options
    • A. decoupling
    • B. filtering
    • C. rectifying
    • D. grounding
    • Discuss
    • 4. How much setup time (ts) is required for the 74LS76?

    • Options
    • A. 5 ns
    • B. 10 ns
    • C. 20 ns
    • D. 40 ns
    • Discuss
    • 5. Can the automatic RC circuit be used to set a flip-flop rather than reset the flip-flop?

    • Options
    • A. yes
    • B. no
    • Discuss
    • 6. In the automatic reset circuit for a flip-flop, how long does it take the capacitor to completely charge?

    • Options
    • A. 1 time constant (RC)
    • B. 2 time constants (RC)
    • C. 5 time constants (RC)
    • D. 10 time constants (RC)
    • Discuss
    • 7. A settable flip-flop's normal starting state when power is first applied to a circuit is always the ________ state.

    • Options
    • A. reset
    • B. set
    • C. toggle
    • D. dual
    • Discuss
    • 8. What is the difference between setup time and hold time?

    • Options
    • A. Setup time occurs after the active clock edge, hold time occurs before the active clock edge.
    • B. Setup time occurs before the active clock edge, hold time occurs after the active clock edge.
    • C. Setup time and hold time both occur at the active clock edge.
    • Discuss
    • 9. Which of the following circuit parameters would be most likely to limit the maximum operating frequency of a flip-flop?

    • Options
    • A. setup and hold time
    • B. clock pulse HIGH and LOW time
    • C. propagation delay time
    • D. clock transition time
    • Discuss
    • 10. Is the propagation delay from the clock to the output for the 7476 the same as the delay from the set or reset to the output?

    • Options
    • A. yes
    • B. no
    • Discuss


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